RM0352 datasheet(92/138 Pages) STMICROELECTRONICS

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I2C bus interface

RM0352

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DocID024647 Rev 1

10.2.12

I2C masked interrupt status register (I2C_MISR)

Table 82. I2C masked interrupt status register (I2C_MISR

)

Address:

I2CBaseAddress + 0x34

Type:

Reset:

0x00000000

[3]

TXFOVR: Tx FIFO overrun. TXFOVR is set when a write operation in the Tx

FIFO is performed and the Tx FIFO is full. The application must avoid

overflow condition by a proper data flow control. Anyway in case of overrun,

the application shall flush the transmitter (I2C_CR:FTX bit to set) because the

Tx FIFO content is corrupted (at least a word has been lost in the FIFO). This

interrupt is cleared setting the related bit of the I2C_ICR register.

0: no overrun condition occurred in the Tx FIFO.

1: overrun condition occurred in the Tx FIFO.

[2]

TXFF: Tx FIFO full. TXFF is set when a full condition occurs in the Tx FIFO

(only for debugging purpose). This bit is self cleared when the Tx FIFO is not

full.

0: Tx FIFO is not full.

1: Tx FIFO is full.

[1]

TXFNE: Tx FIFO nearly empty. TXFNE is set when the number of entries in

the Tx FIFO is less or equal than the threshold value programmed in the

I2CTFTR:THRESHOLD_TX register. It is self cleared when the threshold

level is over the programmed threshold.

0: number of entries in the Tx FIFO greater than the

I2CTFTR:THRESHOLD_TX register.

1: number of entries in the Tx FIFO less or equal than the

I2CTFTR:THRESHOLD_TX register.

[0]

TXFE: Tx FIFO empty. TXFE is set when the Tx FIFO is empty (only for

debugging purpose).

This bit is self cleared writing in the Tx FIFO.

0: Tx FIFO is not empty.

1: Tx FIFO is empty.

I2C masked interrupt status register (I2C_MISR)

27 26 25 24

21 20

19 18 17 16

15 14 13 12 11 10

RESERVED

RRRR

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