| Electronic Components Datasheet Search |
|
RM0352 Datasheet(PDF) 38 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
RM0352 Datasheet(HTML) 38 Page - STMicroelectronics |
|
38 / 138 page ![]() Watchdog timer (WDG) RM0352 38/138 DocID024647 Rev 1 7 Watchdog timer (WDG) The watchdog timer (WDG aka WDT) provides a way of recovering from software crashes. The watchdog clock is used to generate a regular interrupt (WDOGINT), depending on a programmed value. The watchdog monitors the interrupt and asserts a reset signal (WDOGRES) if the interrupt remains unserviced for the entire programmed period. You can enable or disable the watchdog unit as required. The WDG is counting down at a fixed frequency of 32.768 kHz. 7.1 Functionality The watchdog timer is a 32-bit down counter that divides the clock input to produce an interrupt. The divide ratio is fully programmable and controls the interrupt interval, which can be calculated using Equation 1: Equation 1 Interrupt interval = (WDT_LOAD + 1) / (clock frequency in Hz). The default ratio is 4294967296 (equivalent to hex value 0xFFFFFFFF + 1). With a 32.768 kHz watchdog clock this generates an interrupt every ~131072 seconds. This corresponds to the maximum value of WDT_LOAD: 4,294,967,295. If zero is programmed into WDT_LOAD, an interrupt would always be generated immediately. Therefore valid values of WDT_LOAD are 1 or higher. Table 25 shows examples of WDT_LOAD values and the corresponding interrupt interval when using a 32.768 kHz watchdog clock. A watchdog interrupt is generated each time the counter reaches 0. The counter is then reloaded with the content of the WDT_LR register. The interrupt status should be cleared by writing to the interrupt clear register. When the interrupt is cleared, the counter is reloaded with WDT_LOAD value. If the interrupt status is not cleared and a new interrupt is generated, then a watchdog reset is generated, rebooting the system. The watchdog interrupt and reset generation can be enabled or disabled as required by the system using the relevant bits in the control register. When the interrupt generation is Table 25. Interrupt intervals for WDT_LOAD values using a 32 kHz clock WDT_LOAD Interrupt interval (ms) 4294967295 131072000 65535 2000 32767 1000 4095 125 127 3.90625 63 1.953125 10.0610 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |