AN1172

ESD diode conduction due to kick-back

17/23

Appendix B

ESD diode conduction due to kick-back

An over-voltage can appear across the gate and COM (or A1 for triacs) terminals at high

turn-on di/dt rates. This effect is called the "kick-back". It is due to the high density current at

turn-on which causes high conduction voltage drop. Since the conduction begins around the

gate area, the forward voltage is in part applied to the gate.

This gate spike is clamped by the micro-controller internal electrostatic discharge (ESD)

diodes, which can be damaged if conduction lasts for too long.

In order to prevent ESD diodes conduction, their voltage must remain negative. When

considering Figure 1. at ACS turn-on, i.e. when the push transistor M1 is off and the pull

positive. This yields Equation B1.

Equation B1

As M2 is conducting, its voltage drop can be neglected. Thus, the previous relation gives:

Equation B2

If D1 conducts, this means that the supply voltage is held by M2, neglecting D1 drop

voltage. This MOS transistor is thus in a linear mode. Its current equals its saturating level,

controller operation), we can write the following relationship :

Equation B3

This condition, plus Equation B2, gives the following safety rule for no ESD diode

conduction:

Equation B4

0

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