Copyright © 2014 Future Technology Devices International Limited

45

Document No.: FT_000647

FT122 ENHANCED USB DEVICE CONTROLLER WITH PARALLEL

BUS

Clearance No.: FTDI#

313

Appendix A– References

Useful Application Notes

http://www.ftdichip.com/Documents/AppNotes/AN_167_FT1248_Parallel_Serial_Interface_Basics.pdf

http://www.ftdichip.com/Support/Documents/TechnicalNotes/TN_100_USB_VID-PID_Guidelines.pdf

http://www.ftdichip.com/Support/Documents/AppNotes/AN_175_Battery%20Charging%20Over%20USB

%20with%20FTEX%20Devices.pdf

http://www.usb.org/developers/devclass_docs/BCv1.2_011912.zip

Appendix B - List of Figures and Tables

List of Figures

Figure 2-1 FT122 Block Diagram.....................................................................................................3

Figure 3-1 TSSOP-28 package schematic symbol ..............................................................................6

Figure 3-2 QFN-28 package schematic symbol..................................................................................6

Figure 7-1 FT122 bus-powered application ..................................................................................... 32

Figure 7-2 FT122 self-powered application ..................................................................................... 32

Figure 8-1 ALE Timing ................................................................................................................. 36

Figure 8-2 Parallel interface timing ............................................................................................... 37

Figure 8-3 Single cycle DMA timing ............................................................................................... 38

Figure 8-4 Burst mode DMA timing ............................................................................................... 38

Figure 8-5 DMA terminated by EOT_n ........................................................................................... 38

Figure 9-1 TSSOP-28 Package Dimensions ..................................................................................... 39

Figure 9-2 TSSOP-28 Package Markings ........................................................................................ 40

Figure 9-3 QFN-28 Package Dimensions ........................................................................................ 41

Figure 9-4 QFN-28 Package Markings ............................................................................................ 42

Figure 9-5 FT122 Solder Reflow Profile .......................................................................................... 42

List of Tables

Table 3-1 FT122 Pin Description .....................................................................................................8

Table 4-1 Interrupt modes ........................................................................................................... 10

Table 5-1 Endpoint configuration for EP0 and EP1 ........................................................................... 11

Table 5-2 Endpoint configuration for EP2 ....................................................................................... 11

Table 5-3 - Example buffer configuration ....................................................................................... 12

Table 5-4 - Endpoint Maximum Packet Size.................................................................................... 13

Table 6-1 FT122 default command set........................................................................................... 15

Table 6-2 enhanced command set ................................................................................................ 19

Table 6-3 Address Enable Register ................................................................................................ 19

Table 6-4 Endpoint Enable Register............................................................................................... 19

Table 6-5 Configuration Register (Byte 1) ...................................................................................... 20

Table 6-6 Clock Division Factor Register (Byte 2)............................................................................ 21

Table 6-7 DMA Configuration Register (Byte 1)............................................................................... 22

Table 6-8 DMA Endpoint Select Register (Byte 2, for Enhanced Mode) ............................................... 22