DB929B datasheet(26/51 Pages) CMLMICRO

26 / 51 page

4-Level FSK Modem Data Pump

Page 26 of 50

MX929B PRELIMINARY INFORMATION

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otherwise pull the PLL away from its optimum timing. In this case however; it is recommended that the

PLLBW bits only be set to 'Narrow Bandwidth' after the modem has been running in 'Medium Bandwidth'

mode for about 200 symbol times to ensure accurate lock has first been achieved.

The 'Hold' setting disables the feedback loop of the PLL which continues to run at a rate determined only by

the actual crystal frequency and the setting of the Control Register CKDIV bits, not the PLL's operating

frequency immediately prior to the 'Hold' setting.

4.5.4

Mode Register

The contents of this 8-bit write only register control the basic operating modes of the modem:

76543210

Mode Register

IRQEN

RXEYE

SSIEN

INVSYM

SSYM

Tx/Rx

PSAVE

4.5.4.1

Mode Register B7: IRQEN - IRQ Output Enable

When this bit is set to '1', the IRQ chip output pin is pulled low (VSS) given the IRQ bit of the Status Register

is a '1'.

4.5.4.2

Mode Register B6: INVSYM - Invert Symbols

This bit controls the polarity of the transmitted and received symbol voltages.

Symbol

Signal at TXOUT

Signal at RXAMPOUT

'+3'

Above VBIAS

Below VBIAS

'-3'

Below VBIAS

Above VBIAS

'+3'

Below VBIAS

Above VBIAS

'-3'

Above VBIAS

Below VBIAS

Note: B6 must be normally set to the same value in Tx and Rx devices for successful communication between

them.

4.5.4.3

Mode Register B5:

TX/

- Tx/Rx Mode

Setting this bit to '1' places the modem into the Transmit mode, clearing it to '0' puts the modem into the

Receive mode.

Note: Changing between receive and transmit modes will cancel any current task.

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