DB929B datasheet(30/51 Pages) CMLMICRO

30 / 51 page

4-Level FSK Modem Data Pump

Page 30 of 50

MX929B PRELIMINARY INFORMATION

www.mxcom.com Tel: 800 638 5577 336 744 5050

Fax: 336 744 5054

Doc. # 20480171.003

4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA

All trademarks and service marks are held by their respective companies.

The Data Quality readings are only valid when the modem has successfully acquired signal level and timing

lock for at least 64 symbol times. It is invalid when an AQSC or AQLEV sequence is being performed or when

the LEVRES setting is 'Lossy Peak Detect'. A low reading will be obtained if the PLLBW bits are set to 'Wide'

or if the received signal waveform is distorted in any significant way.

Section 5.6 describes how monitoring the Data Quality reading can help improve the overall system

performance in some applications.

4.6

CRC, FEC and Interleaving

4.6.1

Cyclic Redundancy Codes

4.6.1.1

CRC0

This is a six-bit CRC check code used in the Station ID Block. It is calculated by the modem from the first 24

bits of the block (Bytes 0, 1, and 2) as follows:

The 24 bits are considered as the coefficients of a polynomial M(x) of degree 23 such that the MSB bit (7) of

byte 0 is the coefficient of x

23, and bit 0 of byte 2 is the coefficient of x0.

The polynomial F(x) of degree 5 is calculated as being the remainder of the modulo-2 division.

)

(

)

(

The polynomial x

5 + x4 + x3 + x2 + x1 + x0 is added (modulo-2) to F(x).

The coefficients of F(x) are placed in the 6-bit CRC0 field, such that the coefficient of x

5 corresponds to the

MSB of CRC0

4.6.1.2

CRC1

This is a sixteen-bit CRC check code contained in bytes 10 and 11 of the Header Block, which provides error

detection coverage for the Header Block of a message. It is calculated by the modem from the first 80 bits of

the Header Block (Bytes 0 to 9 inclusive) using the generator polynomial:

x16 + x12 + x5 + 1

4.6.1.3

CRC2

This is a thirty-two-bit CRC check code contained in bytes 8 to 11 of the 'Last' Block, which provides error

detection coverage for the combined Intermediate Blocks and Last Block of a message. It is calculated by the

modem from all of the data and pad bytes in the Intermediate Blocks and in the first 8 bytes of the Last Block

using the generator polynomial:

x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x1 + 1

Note: In receive mode the CRC2 checksum circuits are initialized on completion of any task other than NULL

or RILB. In transmit mode the CRC2 checksum circuits are initialized on completion of any task other

than NULL, TIB, or TLB.

Command Register bit B5 (CRC) allows the user to select between two different forms of the CRC0,

CRC1 and CRC2 checksums. When this bit is set to ‘1’ the CRC generators are initialized to ‘all zeros’,

as required by RD-LAP

¥ systems. When this bit is set to '0', the CRC generators are initialized to 'all

ones' for calculations such as CCITT X25 based systems. It should always be set to ‘1’ for RD-LAP

compatibility, other systems may set this bit as required.

4.6.1.4

Forward Error Correction

In transmit mode, the MX929B uses a Trellis Encoder to translate the 96 bits (12 bytes) of a 'Header',

'Intermediate', 'Last' Block, into a 66 symbol (132 bits) sequence which includes FEC information. Station ID

Blocks (30 bits) are translated into a 22 symbol (44 bit) sequence which includes FEC information.

In receive mode, the MX929B decodes the received 22 or 66 symbols of a block into 30 or 96 bits of binary

data using a 'Soft Decision' Viterbi algorithm to perform decoding and error correction.

DB929B Datasheet(PDF) 30 Page - CML Microcircuits

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