DB929B datasheet(16/51 Pages) CMLMICRO

16 / 51 page

4-Level FSK Modem Data Pump

Page 16 of 50

MX929B PRELIMINARY INFORMATION

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Fax: 336 744 5054

Doc. # 20480171.003

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The 'Header' block is self-contained and includes its own checksum (CRC1). It would normally carry

information such as the address of the calling and called parties, the number of following blocks in the frame

(if any), and miscellaneous control information. The number of following blocks (if any) is required to allow the

Rx device software to expect the Last Block and interpret it as a Last Block rather than an Intermediate Block.

There is no other indicator to differentiate a Last Block and an Intermediate Block.

The 'Intermediate' block(s) contain only data, the checksum at the end of the 'Last' block (CRC2) also checks

the data in any preceding 'Intermediate' blocks.

Proprietary systems that do not use RD-LAP

¥ format may use the block structures provided by the MX929B

to build alternative frame formats more suited to the particular application. Some examples are shown in

Figure 7.

SYMBOL

SYNC

SYMBOL

SYNC

SYMBOL

SYNC

FRAME

SYNC

FRAME

SYNC

FRAME

SYNC

'LAST'

BLOCK

'HEADER' BLOCKS

'INTERMEDIATE' BLOCKS

Figure 8: Alternative Frame Structures

The MX929B performs the entire block formatting and de-formatting required to convert data between the

binary form and the Over-Air form as shown in Figure 7.

4.5

The Programmer's View

To the programmer, the modem appears as 4 write only 8-bit registers, shadowed by 3 read only registers.

The individual registers are selected by the A0 and A1 chip inputs:

Write to Modem

Read from Modem

Data Buffer

Command Register

Status Register

Control Register

Data Quality Register

Mode Register

not used

Note: There is a minimum time allowance between accesses of the modem's registers, see Section 6.1.4.

4.5.1

Data Block Buffer

This is a 12-byte read/write buffer used to transfer data (as opposed to command, status, mode, and data

quality or control information) between the modem and the host µC.

To the µC, the Data Block Buffer appears as a single 8-bit register. The modem ensures that sequential µC

reads or writes to the buffer are routed to the correct locations within the buffer.

The µC should only access this buffer when the Status Register BFREE (Buffer Free) bit is '1'.

The buffer should only be written to while in Tx mode and read from while in Rx mode. Note that in receive

mode, the modem will function correctly even if the received data is not read from the Data Buffer by the

PC.

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