DB929B datasheet(25/51 Pages) CMLMICRO

25 / 51 page

4-Level FSK Modem Data Pump

Page 25 of 50

MX929B PRELIMINARY INFORMATION

www.mxcom.com Tel: 800 638 5577 336 744 5050

Fax: 336 744 5054

Doc. # 20480171.003

4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA

All trademarks and service marks are held by their respective companies.

4.5.3.3

Control Register B3, B2: LEVRES - Level Measurement Modes

These two bits have no effect in transmit mode. In receive mode they set the 'normal' or 'steady state'

operating mode of the Rx signal amplitude and DC offset measuring and tracking circuits. These circuits

analyze the Rx signal envelope and charge the DOC1 and DOC2 capacitors to 'store' signal maximum and

minimum references that are used in the data reception process. This setting is temporarily overridden during

the automatic sequencing triggered by an AQLEV command when level is initially being acquired as described

in Section 5.3.

Mode

Hold

Level Track

Lossy Peak Detect

Slow Peak Detect

In normal use the LEVRES bits should be set to '0 1' (Level Track). The other modes are intended for special

purposes, for device testing, or are invoked automatically during an AQLEV sequence.

In 'Slow Peak Detect' modes, the positive and negative excursions of the received signal (after filtering) are

measured by peak rectifiers driving the DOC1 and DOC2 capacitors to establish the amplitude of the signal

and any DC offset with regards to VBIAS. This mode provides good overall performance, particularly when

acquiring level information at the start of a received message, but does not work as well with certain long

sequences of repeated data byte values. It is also susceptible to large amplitude noise spikes, which can be

caused by deep fades.

The 'Lossy Peak Detect' mode is similar to 'Slow Peak Detect' but the capacitor discharge time constant is

much shorter so this mode is not suitable for normal data reception and is only used within part of the

automatic AQLEV acquisition sequence.

In 'Level Track' mode the DOC capacitor voltages are slowly adjusted by the MX929B in such a way as to

minimize the average errors seen in the received signal. This mode provides the best overall performance,

being much more accurate than 'Slow Peak Detect' when receiving large amplitude noise spikes on long

sequences of repeated data byte values. It does, however, depend on the measured levels and timing being

approximately correct. If either of these is significantly wrong then the correction algorithm used by the 'Level

Track' mode can actually drive the voltages on the DOC capacitors away from their optimum levels. For this

reason, the automatic AQLEV acquisition sequence (see Section 5.3) forces the level measuring circuits into

'Slow Peak Detect' mode until a Frame Sync pattern has been found.

In 'HOLD' mode the DOC Capacitors are isolated from the charging and discharging circuits, allowing their

voltages to remain constant.

4.5.3.4

Control Register B1, B0: PLLBW - Phase-Locked Loop Bandwidth Modes

These two bits have no effect in transmit mode. In receive mode, they set the 'normal' or 'steady state'

bandwidth of the Rx clock extraction Phase Locked Loop circuit. The PLL circuit synchronizes itself with the

Rx Signal to develop a local clock signal used in the data clock recovery process. This setting will be

temporarily overridden during the automatic sequencing of an AQSC command when Rx clock extraction

circuits are initially being trained as described in

Section 5.3.

PLL Mode

Hold

Narrow Bandwidth

Medium Bandwidth

Wide Bandwidth

The normal setting for the PLLBW bits should be 'Medium Bandwidth' when the received symbol rate and the

frequency of the receiving modem's crystal are both within

r100ppm of nominal, except at the start of a

symbol clock acquisition sequence (AQSC) when 'Wide Bandwidth' should be selected as described in

Section 5.3.

If the received symbol rate and the crystal frequency are both within

r20ppm of nominal then selection of the

'Narrow Bandwidth' setting will provide better performance especially through fades or noise bursts which may

DB929B Datasheet(PDF) 25 Page - CML Microcircuits

DB929B Datasheet(HTML) 25 Page - CML Microcircuits

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51

Datasheet Download

Link URL