DB929B datasheet(17/51 Pages) CMLMICRO

17 / 51 page

4-Level FSK Modem Data Pump

Page 17 of 50

MX929B PRELIMINARY INFORMATION

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Fax: 336 744 5054

Doc. # 20480171.003

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4.5.2

Command Register

Writing to this register tells the modem to perform a specific task as indicated by the TASK bits and modified

by the AQSC, AQLEV, CRC, and TXIMP bits.

76543210

Command

AQSC

TXIMP Reserved

Set to '0'

TASK

AQLEV CRC

When there is no action to perform, the modem will be in an 'idle' state. If the modem is in transmit mode, the

input to the Tx RRC filter will be connected to VBIAS. In receive mode, the modem will continue to measure

the received data quality and extract symbols from the received signal, supplying them to the de-interleave

buffer, but otherwise these received symbols are ignored.

4.5.2.1

Command Register B7: AQSC - Acquire Symbol Clock

This bit has no effect in transmit mode.

In receive mode, when a byte with the AQSC bit set to '1' is written to the Command Register, and TASK is not

set to RESET, it initiates an automatic sequence designed to achieve symbol timing synchronization with the

received signal as quickly as possible. This involves setting the Phase Locked Loop of the received bit timing

extraction circuits to its widest bandwidth, then gradually reducing the bandwidth as timing synchronization is

achieved, until it reaches the 'normal' value set by the PLLBW bits of the Control Register.

Setting this bit to '0' (or changing it from '1' to '0') has no effect, however; the acquisition sequence will be re-

started every time a byte written to the Command Register has AQSC = '1'.

The use of the symbol clock acquisition sequence is described in Section 5.3.

4.5.2.2

Command Register B6: AQLEV - Acquire Receive Signal Levels

This bit has no effect in transmit mode.

In receive mode, when a byte with the AQLEV bit set to '1' is written to the Command Register and TASK is

not set to RESET, it initiates an automatic sequence designed to measure the amplitude and DC offset of the

received signal as rapidly as possible. This sequence involves setting the measurement circuits to respond

quickly at first, then gradually increasing their response time, therefore improving the measurement accuracy,

until the 'normal' value set by the LEVRES bits of the Control Register is reached.

Setting this bit to '0' (or changing it from '1' to '0') has no effect, however; the acquisition sequence will be re-

started every time a byte written to the Command Register has AQLEV = '1'.

The use of the level measurement acquisition sequence (AQLEV) is described in Section 5.3.

4.5.2.3

Command Register B5: CRC

This bit allows the user to select between two different initial states of the CRC0, CRC1 and CRC2 checksum

generators. When this bit is set to '1' the CRC generators are initialized to 'all zeros', as required by RD-LAP

systems. When this bit is set to ‘0’, the CRC generators are initialized to ‘all ones’ as required by CCITT X25

CRC based systems. It should always be set to '1' for RD-LAP

¥ compatibility. Other systems may set this bit

as required.

4.5.2.4

Command Register B4: TXIMP - Tx Level/Impulse Shape

This bit allows the user to choose between two transmit symbol waveform shapes as described in Section

4.7.

Note: This bit must be set correctly every time the Command Register is written to.

4.5.2.5

Command Register B3 - Reserved

This bit should always be set to '0'.

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