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DB929B Datasheet(PDF) 46 Page - CML Microcircuits

Part # DB929B
Description  Full Data Packet Framing
PDF  51 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  CMLMICRO [CML Microcircuits]
Direct Link  http://www.cmlmicro.com
Logo CMLMICRO - CML Microcircuits

DB929B Datasheet(HTML) 46 Page - CML Microcircuits

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4-Level FSK Modem Data Pump
Page 46 of 50
MX929B PRELIMINARY INFORMATION
©2001 MX-COM, INC.
www.mxcom.com Tel: 800 638 5577 336 744 5050
Fax: 336 744 5054
Doc. # 20480171.003
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
6.1.3.1
Operating Characteristics Notes:
1. Not including any current drawn from the modem pins by external circuitry other than the Xtal oscillator.
2. Small signal impedance.
3. Measured after the external RC filter (R4/C5) for a "+3 +3 -3 -3...." symbol sequence. (Tx output level is
proportional to VDD).
4. Measured at the TXOUT pin with the modem in the Tx idle mode.
5. For optimum performance, measured at RXAMPOUT pin, for a "...+3 +3 -3 -3..." symbol sequence,
TXIMP = 0 or 1. The optimum level and DC offset values are proportional to VDD.
6. Timing for an external input to the XTAL/Clock pin.
7.
WR , RD , CS , A0 and A1 pins.
8. D0 - D7 pins.
9. IRQ pin.
6.1.4
Timing
PC Parallel Interface Timings (ref. Figure 28) Notes
Min.
Typ.
Max.
Units
tACSL
Address valid to CS low time
0
ns
tAH
Address hold time
0
ns
tCSH
CS
hold time
0
ns
tCSHI
CS
high time
1
6.0
clock cycles
tCSRWL
CS
to WR or RD low time
0
ns
tDHR
Read data hold time
0
ns
tDHW
Write data hold time
0
ns
tDSW
Write data setup time
90.0
ns
tRHCSL
RD high to CS low time (write)
0
ns
tRACL
Read access time from CS low
2
175
ns
tRARL
Read access time from RD low
2
145
ns
tRL
RD low time
200
ns
tRX
RD high to D0-D7 3-state time
50
ns
tWHCSL
WR high to CS low time (read)
0
ns
tWL
WR low time
200
ns
6.1.4.1
Timing Notes:
1. Xtal/Clock cycles at the XTAL/CLOCK pin.
2. With 30pF max to VSS on D0 - D7 pins.



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