KAI-4021 datasheet(10/56 Pages) ONSEMI

10 / 56 page

KAI-4021 Image Sensor

www.truesenseimaging.com

Revision 1.1 PS-0014 Pg 10

VERTICAL TO HORIZONTAL TRANSFER

Figure 3: Vertical to Horizontal Transfer Architecture

When the V1 and V2 timing inputs are pulsed, charge in every pixel of the VCCD is shifted one row towards the HCCD.

The last row next to the HCCD is shifted into the HCCD. When the VCCD is shifted, the timing signals to the HCCD must

be stopped. H1 must be stopped in the high state and H2 must be stopped in the low state. The HCCD clocking may

begin THD µs after the falling edge of the V1 and V2 pulse.

Charge is transferred from the last vertical CCD phase into the H1S horizontal CCD phase. Refer to Figure 35 for an

example of timing that accomplishes the vertical to horizontal transfer of charge.

If the fast line dump is held at the high level (FDH) during a vertical to horizontal transfer, then the entire line is

removed and not transferred into the horizontal register.

Top View

Direction of

Vertical

Charge

Transfer

Photo

diode

Transfer

Gate

Fast

Line

Dump

H1S

Direction of

Horizontal

Charge Transfer

Lightshield

not shown

KAI-4021 Datasheet(PDF) 10 Page - ON Semiconductor