MH89770 datasheet(17/36 Pages) MITEL

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Preliminary Information

MH89770

Figure 9 - Reframe Time

1820

2224

Reframe Time (ms)

Percentage Reframe Time Probability Versus Reframe Time

With Pseudo Random Data

ESF

The out of sync threshold can be changed from 2 out

of 4 errors in FT (or FPS) to 4 out of 12 errors in FT

(or FPS). The average reframe time is 24 ms for ESF

mode, and 12ms for D3/D4 modes.

Figure 9 is a bar graph which shows the probability

of achieving frame synchronization at a specific time.

The chart shows the results for ESF mode with CRC

check, and D3/D4 modes of operation. The average

reframe time with random data is 24 ms for ESF, and

13 ms for D3/D4 modes. The probability of a

reframe

time

35 ms or less is

88% for ESF

mode, and 97% for D3/D4 modes. In ESF mode it is

recommended that the CRC check be enabled

unless the line has a high error rate. With the CRC

check disabled the average reframe time is greater

because the framer must also check for mimics.

Applications

1. Typical T1 Application

Figure 10 shows the external components that are

required in a typical T1 application using the

MH89770. The MT8980 is used to control and

monitor the device as well as switch data to DSTi and

DSTo (refer to Application Note MSAN-123 for more

information on the operation of the MT8980). The

MT8952,

HDLC protocol controller, is shown in this

application to illustrate how the data on the FDL

could be used. The digital phase-locked loop, the

MT8941, provides all the clocks

necessary to make

functional

interface.

The

1.544

MHz

clock

extracted by the MH89770 is used to clock in data at

RxT and RxR. It is also internally divided by 193

obtain an 8 kHz clock which is output at E8Ko. The

MT8941 uses this 8 kHz signal to provide a phase

locked 2.048 MHz clock for the ST-BUS interface

and a 1.544 MHz clock for the DS1 transmit side.

Note: the configurations shown in Figures 10 and 12

using the MT8941 may not meet specific jitter

performance requirements. A more sophisticated

PLL may be required for applications designed to

meet specific standards. Please refer to the MT8941

data sheet for further details on its jitter performance.

The split phase unipolar signals output by the

MT8977 at TxA and TxB are used by the line driver

circuit to generate a bipolar AMI signal. The line

driver is transformer coupled to an equalization

circuit

and

the

DS1

line.

Equalization

the

transmitted signal is required to meet AT & T

specifications

for

crossconnect

compatible

equip-ment (see AT&T Technical Advisory #34).

Specifica-tions for the input and output transformers

are shown in Figure 11.

On the receive side the

bipolar line signal is converted into a unipolar format

by the line receiver circuit. The resulting split phase

signals are input at the RxA and RxB pins on the

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