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MH89770 Datasheet(PDF) 21 Page - Mitel Networks Corporation

Part # MH89770
Description  T1/ESF Framer & Interface Preliminary Information
PDF  36 Pages
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Manufacturer  MITEL [Mitel Networks Corporation]
Direct Link  http://www.mitel.com
Logo MITEL - Mitel Networks Corporation

MH89770 Datasheet(HTML) 21 Page - Mitel Networks Corporation

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Preliminary Information
MH89770
Figure 14 - ISDN Voice Data Channel Bank
Digital Line Interface
Switch Matrix
T1 Interface
MT8910
MT8980
MT8910
MT8952
MT8952
MT8952
MT8941
ZT
ZT
DSTo
DSTi
DSTo
DSTi
DSTo
DSTi
DSTo
DSTi
DSTo
DSTi
STi0
STo0
C4i
F0i
STo1
STi1
STo2
STi3
STo3
D-Channel Processing
DSTi
DSTo
CSTi0
CSTo
CSTi1
C2i
C1.5i
OUTA
OUTB
RxR
RxT
E8Ko
F0i
F0i
E8Ko
C4o
C2o
F0o
C1.5
Equal-
izer
µP
µP
µP
µP
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MH89770
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The ISDN channel bank in Figure 14 is divided into
four blocks, the digital line interface, the switch
matrix, the D channel processing, and the T1
interface. Beginning with the digital line interface, the
MT8910
provides
2B+D
160k
bit
bidirectional
communication over single twisted pair wiring. The
MT8910 converts the 160kbit line signal into ST-Bus
format, where it can be manipulated by the MT8980
switch matrix. The data received from the MT8910 is
then transferred to the D channel processor by the
switch matrix. The D channel processor converts the
2B+D format used on the 160 kBit digital line into the
23B+D format used on the T1 Link.
To control and monitor the MT8910s and the T1
interface the switch matrix operates some of its input
and output streams in message mode. This enables
the system to control all of the functions of the
MT8910s and the T1 interface through the Control
ST-BUS points, (CSTi/o).
Clock synchronization is done by the MT8941.
Phase-locked loop # 2 generates ST-BUS clocks that
are synchronized to the extracted 8kHz output from
the T1 interface. Phase-locked loop #1 generates
the transmit T1 clock synchronized to the ST-BUS
clocks, which are synchronized to the extracted T1
clock. This scheme will also allow the system to
operate in a loop timed mode.
With appropriate multiplexing a single D channel
processor can handle all 23 2B+D interfaces. If both
B channels on all 24 lines are going to be used then
it would be necessary to use two T1 trunk interfaces.



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