MH89770 datasheet(3/36 Pages) MITEL

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Preliminary Information

MH89770

DSTi

Data ST-BUS Input: This pin accepts a 2048 kbit/s serial stream which contains the 24

PCM or data channels to be transmitted on the T1 trunk.

C2i

2.048 MHz System Clock (Input): This is the master clock for the ST-BUS section of

the chip. All data on the ST-BUS is clocked in on the falling edge of C2i and out on the

rising edge.

E1.5o

1.544 MHz Extracted Clock (Output): Internally connected to Pin 3.

F0i

Frame Pulse Input: This is the frame synchronization signal which defines the

beginning of the 32 channel ST-BUS frame.

VSS

System ground.

22-24

No Connection.

OUTA

Output A (Open Collector Output): This is the output of the DS1 transmitter circuit. It is

suitable for use with an external pulse transformer to generate the transmit bipolar line

signal.

TxSF

Transmit Superframe Pulse Input: A low pulse applied at this pin will determine the

start of the next transmit superframe as illustrated in Figure 20. The device will free run if

this pin is held high.

RxSF

Received Superframe Pulse Output: A pulse output on this pin indicates that the next

frame of data on the ST-BUS is from frame 1 of the received superframe. The period is

12 frames long in D3/D4 modes and 24 frames in ESF mode. Active only when device is

synchronized to received DS1 signal.

C1.5i

1.544 MHz Clock Input: The rising edge of this clock is used to output data on OUTA,

OUTB. C1.5i must be phase-locked to the C2i system clock.

OUTB

Output B (Open Collector Output): This is the output of the DS1 transmitter circuit. It is

suitable for use with an external pulse transformer to generate the transmit bipolar line

signal.

RxFDL

Received Facility Data Link (Output): A 4 kbit/s serial output stream that is

demultiplexed from the FDL bits in ESF mode, or the received F

S bit pattern when in

SLC96 mode. It is clocked out on the rising edge of RxFDLClk.

DSTo

Data ST-BUS Output: A 2048 kbit/s serial output stream which contains the 24 PCM or

data channels received from the DS1 line.

RxFDLClk

Receive Facility Data Link Clock Output: A 4 kHz clock used to output FDL

information on RxFDL. Data is clocked out on the rising edge of the clock.

VSS

No Connection.

TxFDLClk

Transmit Facility Data Link Clock Output: A 4 kHz clock used to input FDL

information on TxFDL. Data is clocked in on the rising edge of the clock.

No Connection.

TxFDL

Transmit Facility Data Link (Input): A 4 kbit/s serial input stream that is muxed into the

FDL bits in the ESF mode, or the FS pattern when in SLC96 mode. It is clocked in on the

rising edge of TxFDLClk.

No Connection.

LOS

Loss of Signal (Output): This pin goes high when 128 contiguous ZEROs are received

on the RxT and RxR inputs. When LOS is high, RxA and RxB are forced high. LOS is

reset when 48 ones are received in a two T1-frame period.

No Connection.

Pin Description (Continued)

Pin #

Name

Description

MH89770 Datasheet(PDF) 3 Page - Mitel Networks Corporation

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