4-153

Preliminary Information

MH89770

† Timing is over recommended temperature & power supply voltage ranges.

‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.

Figure 21 - DS1 Receive Clock Timing

† Timing is over recommended temperature & power supply voltage ranges.

‡ Typical figures are at 25

°C and are for design aid only; not guaranteed and not subject to production testing.

Figure 22 - ST-BUS Stream Timing

Characteristics

Sym

Min

Max

Units

Test Conditions

1

E1.50 Clock Period

648

ns

2

E1.5o Clock Width High or Low

324

ns

3

E1.5o Clock Rise Time

60

ns

4

E1.5o Clock Fall Time

20

ns

Characteristics

Sym

Min

Max

Units

Test Conditions

1

Serial Output Delay

125

ns

150pF load

2

Serial Input Setup Time

15

ns

3

Serial Input Hold Time

50

ns

DS1 BIT CELLS FOR

RECEPTION

E1.5o

BIT CELL

BIT CELL

Bit Cell Boundaries

C2i

DSTo

or CSTo

DSTi,

CSTi0/CSTi1