MH89770 datasheet(25/36 Pages) MITEL

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4-149

Preliminary Information

MH89770

Figure 17 is divided into three functional blocks

which are the protocol converter, switch matrix, and

T1 interface. The protocol section is dependent on

the particular format that is chosen. In this example it

is assumed that the protocol is HDLC. The Transmit

Clock Enable (TxCEN) and the Receive Clock

Enable (RxCEN) of the MT8952 are active for a

period of 24 consecutive ST-BUS channels, and the

clock speed is 2.048 MHz. This enables the protocol

conversion section to interface directly to the switch

matrix. The switch matrix switches the first 24

channels received from the protocol section into the

24 valid timeslots used by the MH89770. Once the

data enters the T1 interface the MH89770 formats

and transmits the data on the T1 line.

Control and monitoring of the T1 interface is done

through the MT8980 switch matrix. CSTi0 and

CSTo1 are connected to the ST-BUS streams that

are configured for message mode so the controlling

microprocessor can access the Master Control

Words and the Master Status Words.

The received portion of the T1 interface extracts the

data from the T1 stream and formats it into ST-BUS

channels. The MT8980 switches these ST-BUS

channels into the first 24 consecutive channels of an

ST-BUS stream, which is passed to the protocol

conversion block. HDLC packets are disassembled

from the incoming ST-BUS stream by the MT8952.

Clock generation and synchronization are handled

by the MT8941. DPLL #2 generates ST-BUS clocks

that are phase-locked to the extracted 8KHz, and

DPLL #1 generates the transmit T1 clock that is

phase-locked to the ST-BUS frame pulse. Therefore,

the interface is operating in a loop timed mode and

there will be no loss of information due to slips. The

MT8941 can also be configured to operate in a

master timing mode.

8. T1 to CEPT Digital Trunk Converter

The two main digital trunk transmission formats in

use today are T1 and CEPT. Mitel's T1 and CEPT

interfaces convert the digital trunk format into

ST-BUS format. The common element between the

two systems is the ST-BUS.

Therefore, a T1 to

CEPT digital trunk converter can be realized.

Figure 18 shows five blocks which are the T1

interface,

switch

matrix,

CEPT

interface,

clock

generation and synchronization, and DSP Element.

The T1 interface converts the 1.544 MHz serial

stream into the ST-BUS format which interfaces to

the switch matrix through DSTi and DSTo. The CEPT

interface converts the 2.048 MHz serial stream into

the ST-BUS format and interfaces to the switch

matrix through the DSP element.

Figure 18 - T1 to CEPT Digital Trunk Converter

CEPT Interface

MH89790B

DSP

Element

Switch Matrix

T1 Interface

MT8980

MH89770

MT8941

Clock Generator

µP

E8Ki

DPLL #1

DPLL #2

C1.5o

F0o

C2o

C4o

RxA

RxB

F0i

OUTA

OUTB

DSTi

DSTo

CSTi0

CSTi1

CSTo

C2i

E8Ko

STi0

STo0

STo3

STo4

STi4

C4i

F0i

STo1

STi1

STi2

STo2

STo3

DSTi

DSTo

CSTo

CSTi0

CSTi1

F0i

C2i

C1.5i

E8Ko

RxT

RxR

OUTA

OUTB

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