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MT9079AC Datasheet(PDF) 1 Page - Mitel Networks Corporation

Part # MT9079AC
Description  CMOS ST-BUS??FAMILY Advanced Controller for E1
PDF  54 Pages
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Manufacturer  MITEL [Mitel Networks Corporation]
Direct Link  http://www.mitel.com
Logo MITEL - Mitel Networks Corporation

MT9079AC Datasheet(HTML) 1 Page - Mitel Networks Corporation

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4-237
®
Features
•
Meets applicable requirements of CCITT
G.704, G.706, G.732, G.775, G.796, I.431 and
ETSI ETS 300 011
•
HDB3, RZ, NRZ (fibre interface) and bipolar
NRZ line codes
•
Data link access and national bit buffers (five
bytes each)
•
Enhanced alarms, performance monitoring and
error insertion
•
Maskable interrupts for alarms, receive CAS bit
changes, exception conditions and counter
overflows
•
Automatic interworking between CRC-4 and
non-CRC-4 multiframing
•
Dual transmit and receive 16 byte circular
channel buffers
•
Two frame receive elastic buffer with controlled
slip direction indication and 26 channel
hysteresis (208 UI wander tolerance)
•
CRC-4 updating algorithm for intermediate path
points of a message-based data link application
Applications
•
Primary rate ISDN network nodes
•
Digital Access Cross-connect (DACs)
•
CO and PABX switching equipment interfaces
•
E1 add/drop multiplexers and channel banks
•
Test equipment and satellite interfaces
Description
The MT9079 is a feature rich E1 (PCM 30, 2.048
Mbps) link framer and controller that meets the latest
CCITT and ETSI requirements.
The
MT9079
will
interface
to
a
2.048
Mbps
backplane and can be controlled directly by a
parallel processor, serial controller or through the
ST-BUS.
Extensive alarm transmission and reporting, as well
as exhaustive performance monitoring and error
diagnostic features make this device ideal for a wide
variety of applications.
Figure 1 - Functional Block Diagram
TAIS
RxA
RxB
TxA
TxB
TxMF
RxMF
DSTi
DSTo
TxDL
Control
C4i/C2i
F0i
Transmit & Receive
Frame MUX/DEMUX
Data
Interface
Data
Link
Buffer
National
Bit
Buffer
Dual 16
Byte Rx
Buffer
Dual 16
Byte Tx
Buffer
RxDL
DLCLK
Performance
Monitoring &
Control
Interface
Port
Interface
(fig. 3)
ABCD
Signal
Buffer
Test
Code
Gen.
Alarm
PCM 30
Link
Interface
2 Frame Rx
Elastic
Buffer With
Slip Control
÷
256
Phase
Detector
Control
ST-BUS Timing
E2i
E8Ko
Circuit
Timing
Circuit
Timing
VDD
VSS
IC
RESET
to all registers
and counters
(E1)
Ordering Information
MT9079AC
40 Pin Ceramic DIP
MT9079AE
40 Pin Plastic DIP
MT9079AL
44 Pin QFP
MT9079AP
44 Pin PLCC
-40° to 85°C
ISSUE 2
May 1995
MT9079
Advanced Controller for E1
CMOS ST-BUS
™ FAMILY


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