MT9079AC datasheet(6/54 Pages) MITEL

6 / 54 page

MT9079

4-242

Functional Description

The MT9079 is an advanced PCM 30 framer that

meets

supports

the

layer

CCITT

Recommendations of G.703, G.704, G.706, G.775,

G.796 and G.732 for PCM 30; I.431 for ISDN

Primary Rate; and T1.102 for DS1A. It also meets or

supports the layer 1 requirements of ETSI ETS 300

011 and ETS 300 233. Included are all the features

of the MT8979, except for the digital attenuation

ROM and Alternate Digit Inversion (ADI). It also

provides extensive performance monitoring data

collection features.

Control of the MT9079 is achieved through the

hardware

selection

either

parallel

non-multiplexed microprocessor port, an Intel or

Motorola serial controller port, or an ST-BUS port.

The parallel port is based on the signals used by

Motorola microprocessors, but it can also be easily

mated to Intel microprocessors (see the Applications

section of this data sheet).

The serial microcontroller interface of the MT9079

will automatically adapt to either Intel or Motorola

signalling. An ST-BUS interface, consisting of two

control and one status stream, may also be selected,

however, the circular and national bit buffers cannot

be accessed in this mode.

The MT9079 supports enhanced features of the

MT8979. The receive slip buffer hysteresis has been

extended to 26 channels, which is suitable for

multiple trunk applications where large amounts of

wander tolerance is required. The phase status word

has been extended to the one sixteenth bit when the

device is clocked with C4. This provides the

resolution required for high performance phase

locked loops such as those described in MSAN-134.

The received CAS (Channel Associated Signalling)

bits

are

frozen

when

signalling

multiframe

synchronization is lost, and the CAS debounce

duration has been extended to be compliant with

CCITT Q.422.

The MT9079 framing algorithm has been enhanced

to allow automatic interworking between CRC-4 and

non-CRC-4 interfaces. Automatic basic frame alarm

and multiframe alarms have also been added.

The national bits of the MT9079 can be accessed in

three ways. First, through single byte registers;

second, through five byte transmit and receive

national bit buffers; and third, through the data link

pins TxDL, RxDL and DLCLK.

A new feature is the ability to select transparent or

termination modes of operation. In termination mode

the CRC-4 calculation is performed as part of the

framing algorithm. In transparent mode the MT9079

allows the data link maintenance channel to be

modified and updates the CRC-4 remainder bits to

reflect this new data. All channel, framing and

signalling data passes through the device unaltered.

This is useful for intermediate point applications of

an PCM 30 link where the data link data is modified,

but the error information transported by the CRC-4

bits must be passed to the terminating end. See the

Application section of this data sheet.

The MT9079 has a comprehensive suite of status,

alarm,

performance

monitoring

and

reporting

features. These include counters for BPVs, CRC

errors, E-bit errors, errored frame alignment signals,

BERT, and RAI and continuous CRC errors. Also,

included are transmission error insertion for BPVs,

CRC-4 errors, frame and non-frame alignment signal

errors, and loss of signal errors.

Dual transmit and receive 16 byte circular buffers, as

well as line code insertion and detection features

have been implemented and can be associated with

any PCM 30 time slot.

A complete set of loopbacks has been implemented,

which include digital, remote, ST-BUS, payload, and

local and remote time slot.

The functionality of the MT9079 has been heighten

with the addition of a comprehensive set of maskable

interrupts and an interrupt vector function. Interrupt

sources consist of synchronization status, alarm

status, counter indication and overflow, timer status,

slip indication, maintenance functions and receive

channel associated signalling bit changes.

The PCM 30 Interface

PCM 30 (E1) basic frames are 256 bits long and are

transmitted at a frame repetition rate of 8000 Hz,

which results in a aggregate bit rate of 256 bits x

8000/sec.= 2.048 Mbits/sec. The actual bit rate is

2.048 Mbits/sec +/- 50 ppm encoded in HDB3

format. Basic frames are divided into 32 time slots

numbered 0 to 31, see Figure 32. Each time slot is 8

bits in length and is transmitted most significant bit

first (numbered bit 1). This results in a single time

slot data rate of 8 bits x 8000/sec. = 64 kbits/sec.

It should be noted that the Mitel ST-BUS also has 32

channels numbered 0 to 31, but the most significant

bit of an eight bit channel is numbered bit 7 (see

Mitel

Application

Note

MSAN-126).

Therefore,

MT9079AC Datasheet(PDF) 6 Page - Mitel Networks Corporation

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