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MT9079AC Datasheet(PDF) 48 Page - Mitel Networks Corporation |
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MT9079AC Datasheet(HTML) 48 Page - Mitel Networks Corporation |
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48 / 54 page ![]() MT9079 4-284 Notes: 1. The falling edge of DLCLK and IDCLK occurs on the channel 0, bit 4 to bit 3 boundary of every second ST-BUS frame. Figure 20 - Receive Data Link Timing Diagram Figure 21 - Transmit Data Link Timing Diagram AC Electrical Characteristics - Data Link Timing Characteristic Sym Min Typ Max Units Conditions/Notes 1 Data Link Clock Output Delay tDCD 75 ns 150pF, See Note 1 2 Data Link Output Delay tDOD 75 ns 150pF 3 Data Link Setup tDLS 20 ns 4 Data Link Hold tDLH 30 ns C4i C2i RxFDL ST-BUS Bit Stream DLCLK Channel 0, Bit 4 Channel 0, Bit 3 Channel 0, Bit 2 tDCD tDOD VTT VTT VTT, VCT VTT, VCT C4i C2i TxFDL ST-BUS Bit Stream IDCLK* Channel 16, Bit 4 Channel 16, Bit 3 Channel 16, Bit 2 tDCD tDLH tDLS * This clock signal is internal to the MT9079 and cannot be accessed by the user. VTT VTT VTT VTT, VCT |
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