MT9079AC datasheet(35/54 Pages) MITEL

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MT9079

4-271

Bit

Name

Functional Description

RSLIP

Receive Slip. A change of state (i.e.,

1-to-0 or 0-to-1) indicates that a

receive controlled frame slip has

occurred.

RSLPD

Receive Slip Direction. If one, indi-

cates that the last received frame slip

resulted in a repeated frame, i.e.,

system clock (C4i/C2i) faster than

network clock (ECLK). If zero, indi-

cates that the last received frame slip

resulted in a lost frame, i.e., system

clock slower than network clock.

Updated on an RSLIP occurrence

basis.

AUXP

Auxiliary Pattern. This bit will go high

when a continuous 101010... bit

stream (Auxiliary Pattern) is received

on the PCM 30 link for a period of at

least 512 bits. If zero, auxiliary pat-

tern is not being received. This pat-

tern will be decoded in the presents

of a bit error rate of as much as 10-3.

CEFS

Consecutively Errored Frame Align-

ment Signal. This bit goes high when

the last two frame alignment signals

were received in error. This bit will be

low when at least one of the last two

frame alignment signals is without

error.

RxFRM

Receive Frame. The most significant

bit of the phase status word. If one,

the phase status word is greater than

one frame in length; if zero, the

phase status word is less than one

frame in length.

2 - 0

RxTS4-2

Receive Time Slot. The three most

significant bits of a five bit counter

that indicates the number of time

slots between the ST-BUS frame

pulse and E8Ko.

Table 56 - Most Significant Phase Status Word

(Page 3, Address 15H)

Bit

Name

Functional Description

7 - 6

RxTS1-0

Receive Time Slot. The two least sig-

nificant bits of a five bit counter that

indicates the number of time slots

between the ST-BUS frame pulse

and E8Ko.

5 - 3

RxBC2 -0

Receive

Bit

Count.

three

bit

counter that indicates the number of

bits between the

ST-BUS frame

pulse and E8Ko.

2 - 0

RxEBC2 -0 Receive Eighth Bit Count. A three bit

counter that indicates the number of

one

eighth

bit

times

there

are

between the ST-BUS frame pulse

and E8Ko. These least significant

bits are valid only when the device is

clocked at 4.096 MHz. The accuracy

of the this measurement is approxi-

mately + 1/16 (one sixteenth) of a bit.

Table 57 - Least Significant Phase Status Word

(Page 3, Address 16H)

Bit

Name

Functional Description

CRCS1

Receive CRC Error Status One. If

one,

the

evaluation

the

last

received submultiframe one resulted

in an error. If zero, the last submulti-

frame one was error free. Updated

on a submultiframe one basis.

CRCS2

Receive CRC Error Status Two. If

one,

the

evaluation

the

last

received submultiframe two resulted

in an error. If zero, the last submulti-

frame two was error free. Updated on

a submultiframe two basis.

RFAIL

Remote CRC-4 Multiframe Genera-

tor/detector Failure. If one, each of

the previous five seconds have an

E-bit error count of greater than 989,

and for this same period the receive

RAI bit was zero (no remote alarm),

and for the same period the SYNC bit

was equal to zero (basic frame align-

ment has been maintained). If zero,

indicates normal operation.

Table 58 - Alarm Status Word One

(Page 3, Address 19H) (continued)

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