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MT9079AC Datasheet(PDF) 42 Page - Mitel Networks Corporation |
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MT9079AC Datasheet(HTML) 42 Page - Mitel Networks Corporation |
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42 / 54 page ![]() MT9079 4-278 location. The BPV counter is cleared by writing zero to location 1DH first and then writing zero to location 1CH of page 4. The interrupt vector byte is then cleared by reading it. This step ensures that interrupts that occurred when the interface was not initialized will be cleared before the MT9079 IRQ output is activated. The IRQ output function is activated by making SPND low. TAIS is now made high, which indicates to the far end of the link that this end is functional. It should be noted that Figure 12 is an initialization example and does not imply that there is a rigid sequence that must be followed. PCM 30 Trunk and Timing Interface Figure 13 shows the MT9079 connection to a generic Line Interface Unit (LIU). The LIU has three functions: 1) it converts the framed transmit signal to the required PCM 30 pseudo-ternary signal; 2) it converts the received PCM 30 pseudo-ternary signal to a binary signal; and c) it extracts a data clock form the receive PCM 30 signal. In order to meet network requirements, it is necessary to control the transmit equalization of the LIU (EC1 - EC3). This pre-emphasizes the transmit pulse shape so it can fit within a standard pulse template at a specific point on the transmit link. When using a LIU that clocks data in and out with separate signals, the MT9079 remote loopback can allow bit errors to occur. This is because the MT9079 does not re-time the looped signal, so phase differences in the C2 and RCLK clock signals will impact the transmit data. This problem can be prevented by implementing the remote loopback in the LIU and controlling it from a port. Performing the remote loopback in the LIU also more closely adheres to network requirements, which state that a remote loopback should be implemented as close to the PCM 30 side of the trunk as possible. Figure 13 - PCM 30 Line Interface Unit (LIU) Figure 14 - Common Channel Signalling Control (Time Slot 16) through the MC68302 Voice/Data Bus DSTi DSTo F0i C4i/C2i E2i TxA TxB RxA RxB MT9079 EC3 EC2 EC1 RLOOP TCLK to Control Port LIU RCLK E1 Transmit Trunk Interface E1 Receive E8ko System Timing MT8980D STon STin CSTo DTA C4i MT9079 DSTi DSTo C4i/C2i TxA TxB RxA RxB E2i To Trunk Interface MT8980 µP Interface MT9079 µP Interface MC68302 C2 +5V 909 Ω C4 Address Data & Control 100 Ω 100 Ω |
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