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MT9079AC Datasheet(PDF) 41 Page - Mitel Networks Corporation |
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MT9079AC Datasheet(HTML) 41 Page - Mitel Networks Corporation |
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41 / 54 page ![]() MT9079 4-277 The TE control bit sets the state of the transmit E-bits when the receive side has lost CRC-4 synchronization. In this case if the interface is the Terminal Equipment (TE) side, then the E-bits must be zero. If the interface is the Network Termination (NT) side, the transmit E-bits must be one when CRC-4 synchronization is lost. When CRC-4 synchronization is achieved the transmit E-bits will function according to ITU-T G.704. The MT9079 has a suite of 30 maskable interrupts. At this point in the initialization procedure the SYNI, RAII, AISI, AIS16I, LOSI, FERI, BPVO and SLPI interrupts will be unmasked and all others will be masked. If the application does not require interrupts, the SPND control bit should be kept at one. Adjusting the ST-BUS offset will move the bit positions of the ST-BUS output streams with respect to the input frame pulse F0i. This can be used to compensate for large delays in very long backplane applications. It can also be used to minimize the delay through the receive elastic buffer. Selection of the PCM 30 encoding will be determined by the line interface arrangement used. The default is HDB3 encoding on bipolar non-return to zero signals, which will interface directly to most Line Interface Units (LIU). After a power-on reset the state of the error counters of page 4 will be undetermined. Therefore, each of the counters appropriate to the application should be cleared by writing a zero value to the counter Figure 12 - MT9079 Initialization Procedure START TAIS input = low Power-on Reset - RESET input = RC > = 5 x power supply rise time Write 00H to all control SPND bit = 1 registers of pages 7 & 8 Select mode of operation. Note 1. Select National bit, data link, and AIS mode of operation. Note 1. 8KSEL bit = 1 if using the E8Ko output for loop (slave) timing. Note 1. A A is Interface TE? NO Mask and unmask interrupts. Note 1. Select ST-BUS offset. Note 1. Select PCM 30 line encoding. Note 1. Clear the error counters of page 4. Note 2. Read interrupt vector register, page 4. Note 3. SPND = 0. Note 3. TAIS input = high STOP YES TE bit = 1 Notes: 1. Skip if default option is required. 2. Skip if counters are not used. 3. Skip if interrupts are not used. |
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