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MT91L60AS Datasheet(PDF) 24 Page - Mitel Networks Corporation |
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MT91L60AS Datasheet(HTML) 24 Page - Mitel Networks Corporation |
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24 / 32 page ![]() MT91L60/61 Advance Information 24 † Timing is over recommended temperature range & recommended power supply voltages. ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. Note 1: Not production tested, guaranteed by design. AC Electrical Characteristics† - SSI BUS Synchronous Timing (see Figure 12) Characteristics Sym Min Typ‡ Max Units Test Conditions 1 BCL Clock Period tBCL 244 1953 ns BCL=4096 kHz to 512 kHz 2 BCL Pulse Width High tBCLH 115 122 ns BCL=4096 kHz 3 BCL Pulse Width Low tBCLL 122 ns BCL=4096 kHz 4 BCL Rise/Fall Time tR/tF 20 ns Note 1 5 Strobe Pulse Width tENW 8 x tBCL ns Note 1 6 Delayed Strobe Pulse Width tENWD 8 x tBCL ns Note 1 7 Strobe setup time before BCL falling tSSS 70 tBCL-80 ns 8 Strobe hold time after BCL falling tSSH 80 tBCL-80 ns 9 Delayed Strobe Pulse delay after BCL rising tDSTBR 55 ns Note 1 10 Delayed Strobe Pulse hold time after BCL rising tDSTBF 55 ns Note 1 11 Dout High Impedance to Active Low from Strobe rising tDOZL 55 ns CL=50 pF, RL=1K 12 Dout High Impedance to Active High from Strobe rising tDOZH 55 ns CL=50 pF, RL=1K 13 Dout Active Low to High Impedance from Strobe falling tDOLZ 90 ns CL=50 pF, RL=1K 14 Dout Active High to High Impedance from Strobe falling tDOHZ 90 ns CL=50 pF, RL=1K 15 Dout Delay (high and low) from BCL rising tDD 80 ns CL=50 pF, RL=1K 16 Din Setup time before BCL falling tDIS 10 ns 17 Din Hold Time from BCL falling tDIH 50 ns |
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