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MT91L60AS Datasheet(PDF) 26 Page - Mitel Networks Corporation |
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MT91L60AS Datasheet(HTML) 26 Page - Mitel Networks Corporation |
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26 / 32 page ![]() MT91L60/61 Advance Information 26 Figure 13 - SSI Asynchronous Timing Diagram † Timing is over recommended temperature range & recommended power supply voltages. ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. * Note: All conditions → data-data, data-HiZ, HiZ-data. AC Electrical Characteristics† - Microport Timing (see Figure 14) Characteristics Sym Min Typ‡ Max Units Test Conditions 1 Input data setup tIDS 100 ns 2 Input data hold tIDH 30 ns 3 Output data delay tODD 120 ns CL = 50pF, RL = 1K * 4 Serial clock period tCYC 500 1000 ns 5 SCLK pulse width high tCH 250 500 ns 6 SCLK pulse width low tCL 250 500 ns 7 CS setup-Intel tCSSI 200 ns 8 CS setup-Motorola tCSSM 100 ns 9 CS hold tCSH 100 ns 10 CS to output high impedance tOHZ 120 ns CL = 50pF, RL = 1K Din Dout STB 70% 30% 70% 30% 70% 30% Tj tdda1 NOTE: Levels refer to % VDD (CMOS I/O) tdha1 TDATA1 tdda2 TDATA Bit 1 Bit 2 Bit 3 D1 D2 D3 tho tsu TDATA/2 TDATA TDATA |
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