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MT91L60AS Datasheet(PDF) 25 Page - Mitel Networks Corporation |
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MT91L60AS Datasheet(HTML) 25 Page - Mitel Networks Corporation |
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25 / 32 page  Advance Information MT91L60/61 25 Figure 12 - SSI Synchronous Timing Diagram † Timing is over recommended temperature range & recommended power supply voltages. ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. NOTE 1: Not production tested, guaranteed by design. AC Electrical Characteristics† - SSI BUS Asynchronous Timing (note 1) (see Figure 13) Characteristics Sym Min Typ‡ Max Units Test Conditions 1 Bit Cell Period TDATA 7812 3906 ns ns BCL=128 kHz BCL=256 kHz 2 Frame Jitter Tj 600 ns 3 Bit 1 Dout Delay from STB going high tdda1 Tj+600 ns CL=50 pF, RL=1K 4 Bit 2 Dout Delay from STB going high tdda2 600+ TDATA-Tj 600+ TDATA 600 + TDATA+Tj ns CL=50 pF, RL=1K 5 Bit n Dout Delay from STB going high tddan 600 + (n-1) x TDATA-Tj 600 + (n-1) x TDATA 600 + (n-1) x TDATA+Tj ns CL=50 pF, RL=1K n=3 to 8 6 Bit 1 Data Boundary TDATA1 TDATA-Tj TDATA+Tj ns 7 Din Bit n Data Setup time from STB rising tSU TDATA\2 +500ns-Tj +(n-1) x TDATA ns n=1-8 8 Din Data Hold time from STB rising tho TDATA\2 +500ns+Tj +(n-1) x TDATA ns (BCL) Din Dout STB 70% 30% 70% 30% 70% 30% 70% 30% tBCLH tR tF tBCLL tDIS tDIH tDOZL tDD tBCL tDOZH tSSS tENW tSSH tDOLZ tDOHZ NOTE: Levels refer to % VDD (CMOS I/O) CLOCKin 70% 30% STBd tENWD tDSTBR tDSTBF |
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