Advance Information

MT91L60/61

7

When 0, D-Channel data is shifted at the rate of 2

bits/frame (16 kb/s default).

16 kb/s D-Channel operation is the default mode

which allows the microprocessor access to a full byte

of D-Channel information every fourth ST-BUS

frame. By arbitrarily assigning ST-BUS frame n as

the

reference

frame,

during

which

the

microprocessor D-Channel read and write operations

are performed, then:

Figure 4 - Serial Port Relative Timing for Intel Mode 0

Figure 5 - Serial Port Relative Timing for Motorola Mode 00/National Microwire

XX

R/W

Œ

Delays due to internal processor timing which are transparent.

y

The MT91L60/L61:latches received data on the rising edge of SCLK.

Ž

The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The



A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.



The COMMAND/ADDRESS byte contains:

Œ

Ž





Œ

y

Ž



COMMAND/ADDRESS

DATA INPUT/OUTPUT

COMMAND/ADDRESS:

DATA 1

RECEIVE

DATA 1

TRANSMIT

SCLK

CS

-outputs transmit data on the falling edge of SCLK.

subsequent byte is always data until terminated via CS returning high.

1 bit - Read/Write

3 bits - Addressing Data

4 bits - Unused

XX

Œ

Ž



Œ

y

Ž



COMMAND/ADDRESS

DATA INPUT/OUTPUT

COMMAND/ADDRESS:

DATA 2

RECEIVE

DATA 1

TRANSMIT

SCLK

CS

R/WX

X

Œ

Delays due to internal processor timing which are transparent .

Ž

The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The



A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.



The COMMAND/ADDRESS byte contains:

subsequent byte is always data until terminated via CS returning high.

1 bit - Read/Write

3 bits - Addressing Data

4 bits - Unused



y

The MT91L60/L61: latches received data on the rising edge of SCLK.

-outputs transmit data on the falling edge of SCLK.

XX