MT91L60AS datasheet(4/32 Pages) MITEL

4 / 32 page

MT91L60/61

Preliminary Information

In the event of PWRST, the MT91L60/61 defaults

such that the side-tone path is off, all programmable

gains are set to 0dB and ITU-T

µ-Law is selected.

Further, the digital port is set to SSI mode operation

at 2048 kb/s and the FDI and driver sections are

powered up. (See Microport section.)

The internal architecture is fully differential to provide

the best possible noise rejection as well as to allow a

wide dynamic range from a single 3 volt supply

design.

This

fully

differential

architecture

continued into the Transducer Interface section to

provide full chip realization of these capabilities for

the handset functions.

A reference voltage (VRef), for the conversion

requirements of the Codec section, and a bias

voltage (VBias), for biasing the internal analog

sections, are both generated on-chip. VBias is also

brought to an external pin so that it may be used for

biasing external gain setting ampliﬁers. A 0.1

µF

capacitor must be connected from VBias to analog

ground at all times. Although VRef may only be used

internally, a 0.1

µF capacitor must be connected from

VRef to ground. The analog ground reference point

for these two capacitors must be physically the same

point. To facilitate this the VRef and VBias pins are

situated on adjacent pins.

The transmit ﬁlter is designed to meet ITU-T G.714

speciﬁcations. The nominal gain for this ﬁlter is 0dB

(gain control = 0dB). Gain control allows the output

signal to be increased up to 7dB. An anti-aliasing

ﬁlter is included. This is a second order lowpass

implementation with a corner frequency at 25 kHz.

The receive ﬁlter is designed to meet ITU-T G.714

speciﬁcations. The nominal gain for this ﬁlter is 0dB

(gain control = 0dB). Gain control allows the output

signal to be attenuated up to 7dB. Filter response is

peaked to compensate for the sinx/x attenuation

caused by the 8 kHz sampling rate.

Side-tone is derived from the input of the Tx ﬁlter and

is not subject to the gain control of the Tx ﬁlter

section. Side-tone is summed into the receive

handset transducer driver path after the Rx ﬁlter gain

control section so that Rx gain adjustment will not

affect side-tone levels. The side-tone path may be

enabled/disabled with the gain control bits located in

Gain Control Register 2 (address 01h).

Transmit and receive ﬁlter gains are controlled by the

TxFG0-TxFG2 and RxFG0-RxFG2 control bits,

respectively. These are located in Gain Control

adjustable from 0dB to +7dB and receive ﬁlter gain

from 0dB to -7dB, both in 1dB increments.

Side-tone ﬁlter gain is controlled by the STG0-STG2

control bits located in Gain Control Register 2

(address 01h). Side-tone gain is adjustable from

-9.96dB to +9.96dB in 3.32dB increments.

Companding law selection for the Filter/Codec is

provided by the A/

µ companding control bit while

the coding scheme is controlled by the Smag/ITU-T

control bit. The A/

µ control bit is logically OR’ed with

the A/

µ pin providing access in both controller and

controllerless modes.

Both A/

µ and Smag/ITU-T

reside in Control Register 2 (address 04h). Table 1

illustrates these choices.

Table 1

Transducer Interfaces

Standard handset transducer interfaces are provided

by the MT91L60/61. These are:

• The handset microphone inputs (transmitter),

pins M+/M-. The nominal transmit path gain may

be adjusted to either 6.0 dB or 15.3 dB. Control of

this gain is provided by the TxINC

control bit

(Gain Control register 1, address 00h).

• The handset speaker outputs (receiver), pins

HSPKR+/HSPKR-. This internally compensated

fully differential output driver is capable of driving

the load shown in Figure 3. The nominal receive

path gain may be adjusted to either 0 dB, -6 dB or

-12 dB. Control of this gain is provided by the

RxINC control bit (Gain Control register 1,

address 00h). This gain adjustment is in addition

to the programmable gain provided by the receive

ﬁlter.

Microport

The serial microport, compatible with Intel MCS-51

(mode 0), Motorola SPI (CPOL=0,CPHA=0) and

Code

Sign/

Magnitude

ITU-T (G.711)

µ-Law

A-Law

+ Full Scale

1111 1111

1000 0000

1010 1010

+ Zero

1000 0000

1111 1111

1101 0101

-Zero

(quiet code)

0000 0000

0111 1111

0101 0101

- Full Scale

0111 1111

0000 0000

0010 1010

Intel® and MCS-51® are registered trademarks of Intel Corporation

Motorola® and SPI® are registered trademarks of Motorola Corporation

National® and Microwire® are trademarks of National Semiconductor Corporation

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