LXT351 datasheet(23/46 Pages) INTEL

23 / 46 page

T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT351

Datasheet

2.5.4.5

Built-In Self Test

LXT351 provides a Built-In Self Test (BIST) capability. The BIST exercises the internal circuits by

providing an internal QRSS pattern, running it through the encoders and the transmit drivers then

looping it back through the receive equalizer, jitter attenuator and decoders to the QRSS pattern

detection circuitry. If all the blocks in this data path function correctly, the receive pattern detector

locks onto the pattern. It then pulls INT Low and sets the following bits:

• TSR.TQRSS = 1

• PSR.QRSS = 1

• PSR.BIST = 1

Note that during BIST, the TPOS/TNEG inputs must remain at logic level = 0

The most reliable test will result when a separate TCLK and MCLK are applied.

2.6

Parallel Microprocessor Interface

The LXT351 multiplexed address/data bus and timing/control signals are compatible with both the

Intel and Motorola microprocessors. See Figure 16 and Figure 17 for the I/O timing diagram for

each bus. The LXT351 detects and distinguishes between Intel and Motorola timing and then

automatically selects the appropriate bus timing. The maximum recommended processor speed for

an Intel device is 20 MHz; for a Motorola device, 16.78 MHz. See “Test Specifications” on

page 33 for microprocessor interface timing details.

The LXT351 contains five read/write and two read-only registers for control and status purposes.

Table 6 on page 24 is a summary of the registers. Table 7 through Table 14 identify and explain the

function of the register bits.

2.6.1

Interrupt Handling

The LXT351 provides a latched interrupt output pin (INT). When enabled, a change in any of the

Performance Status Register bits will generate an interrupt. An interrupt can also be generated

when the elastic store overflows (TSR.ESOVR) or underflows (TSR.ESUNF). When an interrupt

occurs, the INT output pin is pulled Low. Note that the output stage of the INT pin has internal

pull-down only. Therefore, each device that shares the INT line requires an external pull-up

resistor.

The interrupt is cleared when the interrupt condition no longer exists, and the host processor writes

a 1 to the respective interrupt causing bit(s) in the Interrupt Clear Register (ICR). Leaving a 1 in

any of the ICR bits masks that interrupt. To re-enable an interrupt bit, write a 0.

LXT351 Datasheet(PDF) 23 Page - Intel Corporation