LXT351 datasheet(39/46 Pages) INTEL

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T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT351

Datasheet

Table 30. 20 MHz Intel Bus Parallel I/O Timing Characteristics (See Figure 16)

Parameter

Sym

Min

Max

Unit

Test Conditions

ALE pulse width

TLHLL

–

Address valid to ALE falling edge

TAVLL

–

ALE falling edge to address hold time

TLLAX

–

ALE falling edge to RD falling edge

TLLRL

–

ALE falling edge to WR falling edge

TLLWL

–

CS falling edge to RD falling edge

TCLRL

–

CS falling edge to WR falling edge

TCLWL

–

RD Low pulse width

TRLRH

–

RD falling edge to data valid

TRLDV

Data hold time after RD rising edge

TRHDX

535

RD rising edge to ALE rising edge

TRHLH

–

RD rising edge to address valid

TRHAV

–

CS Low hold time after RD rising edge

TRHCH

–

WR Low pulse width

TWLWH

–

Data setup time before WR rising edge

TDVWH

–

Data hold time after WR rising edge

TWHDX

–

WR rising edge to ALE rising edge

TWHLH

–

CS Low hold time after WR rising edge

TWHCH

–

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