LXT351 datasheet(28/46 Pages) INTEL

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LXT351 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation

Datasheet

5DFMO

1 = Driver Failure Monitor Open detected.

0 = Driver Failure Monitor Open not detected.

6BIST

1 = Built-In Self Test passed.

0 = Built-In Self Test did not pass (or was not run).

Reserved. Ignore.

Table 14. Control Register #4 Read/Write, Address (A7-A0) = x010111x

Bit

Name

Function

0CODEV

1 = Enable detection of HDB3 code violations at the BPV pin along with bipolar violations and Zero

Substitution Violations (if enabled).

0 = Disable detection of HDB3 code violations

1ZEROV

1 = Enable detection of HDB3 Zero Substitution Violations (four consecutive zeros). Note that Zero

Substitution Violations are reported at the BPV pin.

0 = Disable detection of HDB3 Zero Substitution Violations.

LOS2048

1 = Set LOS detection threshold to 2048 consecutive zeros.

0 = Set LOS detection threshold to 32 consecutive zeros (for E1 operation) or to 175 consecutive

zeros (for T1 operation).

COL32CM

1 = Set LOS clear condition criterion to receipt of 32 consecutive marks (E1 operation).

0 = Set LOS clear condition criterion to 12.5% mark density (E1 operation).

Reserved. Set to 0 for normal operation, ignore when reading

Table 13. Performance Status Register Read Only, Address (A7-A0) = x010101x

Bit

Name

Function

LXT351 Datasheet(PDF) 28 Page - Intel Corporation