DS2143 datasheet(27/44 Pages) DALLAS

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DS2143/DS2143Q

27 of 44

RCBR1/RCBR2/RCBR3/RCBR4:

RECEIVE CHANNEL BLOCKING REGISTERS (Address=2B to 2E Hex)

(MSB)

(LSB)

CH8

CH7

CH6

CH5

CH4

CH3

CH2

CH1

RCBR1 (2B)

CH16

CH15

CH14

CH13

CH12

CH11

CH10

CH9

RCBR2 (2C)

CH24

CH23

CH22

CH21

CH20

CH19

CH18

CH17

RCBR3 (2D)

CH32

CH31

CH30

CH29

CH28

CH27

CH26

CH25

RCBR4 (2E)

SYMBOL

POSITION

NAME AND DESCRIPTION

CH32

RCBR4.7

Receive Channel Blocking Registers.

0 = force the RCHBLK pin to remain low during this channel

time.

CH1

RCBR1.0

1 = force the RCHBLK pin high during this channel time.

TCBR1/TCBR2/TCBR3/TCBR4:

TRANSMIT CHANNEL BLOCKING REGISTERS (Address=22 to 25 Hex)

(MSB)

(LSB)

CH8

CH7

CH6

CH5

CH4

CH3

CH2

CH1

TCBR1 (22)

CH16

CH15

CH14

CH13

CH12

CH11

CH10

CH9

TCBR2 (23)

CH24

CH23

CH22

CH21

CH20

CH19

CH18

CH17

TCBR3 (24)

CH32

CH31

CH30

CH29

CH28

CH27

CH26

CH25

TCBR4 (25)

SYMBOL

POSITION

NAME AND DESCRIPTION

CH32

TCBR4.7

Receive Channel Blocking Registers.

0 = force the TCHBLK pin to remain low during this channel

time.

CH1

TCBR1.0

1 = force the TCHBLK pin high during this channel time.

10.0 ELASTIC STORE OPERATION

The DS2143 has an onboard two-frame (512 bits) elastic store. This elastic store can be enabled via

RCR2.1. If the elastic store is enabled (RCR2.1=1), then the user must provide either a 1.544 MHz

(RCR2.2=0) or 2.048 MHz (RCR2.2=1) clock at the SYSCLK pin. If the elastic store is enabled, then the

user has the option of either providing a frame sync at the RFSYNC pin (RCR1.5=1) or having the

RFSYNC pin provide a pulse on frame or multiframe boundaries (RCR1.5=0). If the user wishes to

obtain pulses at the frame boundary, then RCR1.6 must be set to 0, and if the user wishes to have pulses

occur at the multiframe boundary, then RCR1.6 must be set to 1. If the user selects to apply a 1.544 MHz

clock to the SYSCLK pin, then every fourth channel will be deleted and the F-bit position inserted

(forced to 1). Hence channels 1, 5, 9, 13, 17, 21, 25, and 29 (timeslots 0, 4, 8, 12, 16, 20, 24, and 28) will

be deleted. Also, in 1.544 MHz applications, the RCHBLK output will not be active in channels 25

through 32 (or in other words, RCBR4 is not active). See Section 13 for more details. If the 512-bit

elastic buffer either fills or empties, a controlled slip will occur. If the buffer empties, then a full frame of

data (256 bits) will be repeated at RSER and the SR1.4 and RIR.3 bits will be set to a 1. If the buffer fills,

then a full frame of data will be deleted and the SR1.4 and RIR.4 bits will be set to a 1.

DS2143 Datasheet(PDF) 27 Page - Dallas Semiconductor

DS2143 Datasheet(HTML) 27 Page - Dallas Semiconductor

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