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DS2143 Datasheet(PDF) 32 Page - Dallas Semiconductor

Part # DS2143
Description  E1/ISDN-PRI framing transceiver
PDF  44 Pages
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Manufacturer  DALLAS [Dallas Semiconductor]
Direct Link  https://www.maximintegrated.com/en.html
Logo DALLAS - Dallas Semiconductor

DS2143 Datasheet(HTML) 32 Page - Dallas Semiconductor

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DS2143/DS2143Q
32 of 44
RECEIVE SIDE 2.048 MHZ BOUNDARY TIMING
(WITH ELASTIC STORE ENABLED)
NOTES:
1. RSYNC is in the output mode (RCR1.5=0).
2. RSYNC is in the input mode (RCR1.5=1).
3. RCHBLK is programmed to block channel 1.
RECEIVE SIDE BOUNDARY TIMING
(WITH ELASTIC STORE DISABLED)
NOTES:
1. There is a 6 RCLK delay from RPOS, RNEG to RSER.
2. RCHBLK is programmed to block channel 2.
3. RLINK is programmed to output the Sa4 bits.
4. RLINK is programmed to output the Sa4 and Sa8 bits.
5. RLINK is programmed to output the Sa5 and Sa7 bits.
6. Shown is a non-align frame boundary.



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