DS2143 datasheet(28/44 Pages) DALLAS

28 / 44 page

DS2143/DS2143Q

28 of 44

11.0 ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION

The DS2143 provides for access to both the Additional (Sa) and International (Si) bits. On the receive

side, the RAF and RNAF registers will always report the data as it received in the Additional and

International bit locations. The RAF and RNAF registers are updated with the setting of the Receive

Align Frame bit in Status Register 2 (SR2.6). The host can use the SR2.6 bit to know when to read the

RAF and RNAF registers. It has 250

µs to retrieve the data before it is lost.

On the transmit side, data is sampled from the TAF and TNAF registers with the setting of the Transmit

Align Frame bit in Status Register 2 (SR2.3). The host can use the SR2.3 bit to know when to update the

TAF and TNAF registers. It has 250

µs to update the data or else the old data will be retransmitted. Data

in the Si bit position will be overwritten if either the DS2143 is programmed: (1) to source the Si bits

from the TSER pin, (2) in the CRC4 mode, or (3) have automatic E-bit insertion enabled. Data in the Sa

bit position will be overwritten if any of the TCR2.3 to TCR2.7 bits is set to 1. Please see the register

descriptions for TCR1 and TCR2 and the Transmit Data Flow diagram in Section 13 for more details.

RAF: RECEIVE ALIGN FRAME REGISTER (Address=2F Hex)

(MSB)

(LSB)

00110

SYMBOL

POSITION

NAME AND DESCRIPTION

RAF.7

International Bit.

RAF.6

Frame Alignment Signal Bit.

RAF.5

Frame Alignment Signal Bit.

RAF.4

Frame Alignment Signal Bit.

RAF.3

Frame Alignment Signal Bit.

RAF.2

Frame Alignment Signal Bit.

RAF.1

Frame Alignment Signal Bit.

RAF.0

Frame Alignment Signal Bit.

DS2143 Datasheet(PDF) 28 Page - Dallas Semiconductor