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DS2143 Datasheet(PDF) 33 Page - Dallas Semiconductor

Part # DS2143
Description  E1/ISDN-PRI framing transceiver
PDF  44 Pages
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Manufacturer  DALLAS [Dallas Semiconductor]
Direct Link  https://www.maximintegrated.com/en.html
Logo DALLAS - Dallas Semiconductor

DS2143 Datasheet(HTML) 33 Page - Dallas Semiconductor

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DS2143/DS2143Q
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G.802 TIMING
NOTE:
1. RCHBLK/TCHBLK is programmed to pulse high during timeslots 1 to 15, 17 to 25, during bit 1 of
timeslot 26.
TRANSMIT SIDE BOUNDARY TIMING
NOTES:
1. There is a 5 TCLK delay from TSER to TPOS, and TNEG.
2. TSYNC is in the input mode (TCR1.0=0).
3. TSYNC is in the output mode (TCR1.0=1).
4. TCHBLK is programmed to block channel 2.
5. TLINK is programmed to source the Sa4 bits.
6. TLINK is programmed to source the Sa7 and Sa8 bits.
7. Shown is a non-align frame boundary.



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