AD9786 datasheet(29/60 Pages) AD

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AD9786

Rev. 0 | Page 29 of 60

AD9786 Low Setup/Hold Mode (DATACLK input, data

recovery off)

Some applications may require that digital input data be

synchronized with the DATACLK input, rather than DACCLK.

For these applications, the AD9786 can be programmed for Low

Setup/Hold Mode by entering the values in Table 26 into the

SPI registers. With data recovery off and the MODSYNC bit set

to logic 1, the AD9786 will latch data in on the rising or falling

edge of DATACLK input, depending on the state of DCLKPOL.

The timing is similar to the slave mode with data recovery on.

There is still a required timing relationship between DACCLK

and DATACLK in, as shown in Figure 51 and Figure 52. As

these show, the digital input data is latched in on the

DATACLK edge, rather than DACCLK. One advantage of this

mode is that the setup and hold numbers for the input data with

respect to DATACLK are much smaller than the similar specs in

the slave/clock recovery mode.

Note that in this mode, the DATAADJ bits have no effect.

tHT = 0.0ns MIN

tS = –1.1ns MIN

tH = 2.8ns MIN

DACCLKIN

DATACLKIN

DATA

tST = 3.0ns MIN

Figure 51. Low Setup and Hold Mode Timing, 2× Interpolation, DCLKPOL = 0

DACCLKIN

DATACLKIN

DATA

tS = –1.8ns MIN

tH = 3.1ns MIN

tHT = 1.0ns MIN

tST = 2.0ns MIN

Figure 52. Low Setup and Hold Mode Timing, 2× Interpolation, DCLKPOL = 1

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