AD9786 datasheet(31/60 Pages) AD

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AD9786

Rev. 0 | Page 31 of 60

Note that the data in Figure 44 to Figure 53 was taken with the

DATAADJ default of 0000. With DCLKPOL = 0, the latching

edge of DACCLK is just previous to the rising edge of

DATACLK; with DCLKPOL = 1, the latching edge of DACCLK

is just previous to the falling edge of DATACLK. Table 27

describes the values available for 8× interpolation which gives a

choice of 16 edges to sync data. With 4× interpolation, there will

be a choice of 8 edges, and the relevant values from Table 27 will

be 0000, 0010, 0100, 0110, 1000, 1010, 1100, and 1110. These

options will allow latching edge placement from +3 cycles to

–4 cycles. In 2× interpolation, 4 edges will be available, and the

relevant values from Table 27 will be 0000, 0100, 1000, and 1100.

The choices for DATAADJ are diminished to +1 cycle to

–2 cycles.

Figure 54, Figure 55, and Figure 56 show the alignment for the

latching edge of DACCLK with 4× interpolation and different

settings for DATAADJ. In Figure 54, the AD9786 is in

DATACLK Master Mode. DATAADJ is set to 0000, with

DCLKPOL set to 0 so that the latching edge of DACCLK is

immediately before the rising edge of DATACLK. The data

transitions shown in Figure 54 are synchronous with the

DACCLK, so that DACCLK and input data are constant with

respect to each other. The only visible change when DATAADJ

is altered is that DATACLK moves, indicating the latching edge

has moved as well. Note that in DATACLK Master Mode, when

DATAADJ is altered, the latching edge with respect to

DATACLK remains the same.

RISING EDGE OF DATACLK

CONCURRENT WITH

LATCHING EDGE OF DACCLK

DATA TRANSITION

DACCLK

LATCHING EDGE

Figure 54. DATAADJ = 0000

Figure 55 shows the same conditions, but with DATAADJ set to

1111. This moves DATACLK to the left in the plot, indicating

that it occurs one DACCLK cycle before it did in Figure 54. As

explained previously, the latching edge of DACCLK also moves

one cycle back in time.

RISING EDGE OF DATACLK

CONCURRENT WITH

LATCHING EDGE OF DACCLK

DATA TRANSITION

DACCLK

LATCHING EDGE

Figure 55. DATAADJ = 1111

Figure 56 shows the same conditions, with DATAADJ set to

0001, thus moving DATACLK to the right in the plot. This

indicates that it occurs one DACCLK cycle after it did in

Figure 54. In this case, the latching edge of DACCLK moves

forward in time one cycle.

RISING EDGE OF DATACLK

CONCURRENT WITH

LATCHING EDGE OF DACCLK

DATA TRANSITION

DACCLK

LATCHING EDGE

Figure 56. DATAADJ = 0001

AD9786 Datasheet(PDF) 31 Page - Analog Devices

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