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WM8993 Datasheet(PDF) 199 Page - Wolfson Microelectronics plc

Part # WM8993
Description  Audio Hub CODEC for Multimedia Phones
PDF  229 Pages
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Manufacturer  WOLFSON [Wolfson Microelectronics plc]
Direct Link  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8993 Datasheet(HTML) 199 Page - Wolfson Microelectronics plc

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Production Data
WM8993
w
PD, November 2010, Rev 4.0
199
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R64 (40h)
FLL Control
5
12:7
FLL_FRC_NC
O_VAL [5:0]
00_0000
Forces the oscillator value
Valid range is 000000 to 111111
0x19h (011001) = 12MHz approx
(Note that this field is required for free-running FLL
modes only)
6
FLL_FRC_NC
O
0
FLL control select
0 = controlled by digital loop (default)
1 = controlled by FLL_FRC_NCO_VAL
(Note that this field is required for free-running FLL
modes only)
4:3
FLL_CLK_REF
_DIV [1:0]
00
FLL Clock Reference Divider
00 = MCLK / 1
01 = MCLK / 2
10 = MCLK / 4
11 = MCLK / 8
MCLK (or other input reference) must be divided down
to <=13.5MHz.
For lower power operation, the reference clock can be
divided down further if desired.
1:0
FLL_CLK_SRC
[1:0]
10
FLL Clock source
00 = MCLK
01 = LRCLK
10 = BCLK
11 = Reserved
Register 40h FLL Control 5
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R65 (41h)
Clocking 3
13:10
CLK_DCS_DIV
[3:0]
1000
DC Servo Clock Divider
0000 = CLK_SYS
0001 = CLK_SYS / 1.5
0010 = CLK_SYS / 2
0011 = CLK_SYS / 2.5
0100 = CLK_SYS / 3
0101 = CLK_SYS / 4
0110 = CLK_SYS / 5.5
0111 = CLK_SYS / 6
1000 = CLK_SYS / 8
Note - this field is ignored and invalid in Automatic
Clocking Configuration mode.
9:7
SAMPLE_RAT
E [2:0]
101
Selects the Sample Rate (fs)
000 = 8kHz
001 = 11.025kHz, 12kHz
010 = 16kHz
011 = 22.05kHz, 24kHz
100 = 32kHz
101 = 44.1kHz, 48kHz
4:1
CLK_SYS_RA
TE [3:0]
0011
Selects the CLK_SYS / fs ratio
0000 = 64
0001 = 128
0010 = 192
0011 = 256



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