LM3559 datasheet(17/50 Pages) TI1

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LED Current

VIN

Flash Current Target = 1125 mA

32 Ps

VIN Flash

Monitor

Threshold

Flash Current Limited to 900 mA

LM3559

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SNVS624B – JUNE 2011 – REVISED JUNE 2016

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Feature Description (continued)

To avoid noise from falsely triggering the VIN flash monitor, this mode incorporates an 8-µs deglitch timer as well

as an internal analog filter at the input of the VIN flash monitor comparator. With the VIN flash monitor active, VIN

must go below the VIN flash monitor threshold (VIN_FLASH) and remain below it for 8 µs before the flash current

ramp is halted and the VIN flash monitor flag is written.

8.3.8 Last Flash Register

Once the VIN flash monitor is tripped, the flash code that corresponded to the LED current at which the flash

current ramp was halted is written to the Last Flash Register. The Last Flash Register is a read-only register; the

lower 4 bits are available to latch the code for LED1 and the upper 4 bits to latch the code for LED2.

For example, suppose that the LM3559 device is set up for a single LED with a target flash current of 1125 mA.

The VIN flash monitor is enabled with the VIN flash monitor threshold set to 3. V (VIN Monitor Register bits [5:4] =

0, 1). When the STROBE input is brought high, the LED current begins ramping up through the torch and flash

codes at 32 µs per code. As the input current increases, the input voltage at the device IN pin begins to fall due

to the source impedance of the battery. By the time the LED current has reached 900 mA (code 0x77 or 450 mA

per current source), VIN falls below 3 V. The VIN flash monitor then stops the flash current ramp and the device

continues to proceed with the flash pulse, but at 900 mA instead of 1125 mA. Figure 31 details this sequence.

Figure 31. VIN Flash Monitor Example

8.3.9 LED Voltage Monitor

The LM3559 includes a 4-bit ADC which monitors the LED forward voltage (VLED) and stores the digitized value

in bits [3:0] of the VLED Monitor Register. The highest voltage of VLED1 or VLED2 is automatically sensed and

that becomes the sample point for the ADC. Bit 5, the ADC shutdown bit, enables or disables the ADC with the

default state set to enable (bit [5] = 0).

8.3.10 ADC Delay

The ADC Delay Register provides for a programmable delay from 250 µs to 8 ms, in steps of 250 µs. This delay

is the delay from when the EOC bit goes low to when the VLED monitor samples the LED voltage. In automatic

mode the EOC bit goes low when the Flash LED current hits its target. In manual mode the EOC bit goes low at

the end of a readback of the VLED Monitor Register (or when the manual mode bit (bit 4) is re-written with a 1).

Figure 32 and Figure 33 detail the timing of the VLED Monitor for both automatic mode and manual mode.

LM3559 Datasheet(PDF) 17 Page - Texas Instruments