SLMA002 datasheet(22/46 Pages) TI1

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OUT

DIODE

d =

(14)

Light Load Operation

DCM =

´ d ´

OUT

(15)

Inductor

Current

OUT

Ripple

SW Waveform

Steady State

= 12 V

OUT

= 5 V

SW Waveform

OUT

Ripple

Inductor

Current

Skipping

= 12 V

OUT

= 5 V

SW Node Ringing

TPS55383

,, TPS55386

SLUS818 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com

DESIGN HINT

Ensure that under ALL conditions of line and load regulation, there is sufficient duty

cycle to maintain output voltage regulation.

To calculate the operating duty cycle, use Equation 14.

where

• V

DIODE is the forward voltage drop of the rectifier diode

There is no special circuitry for pulse skipping at light loads. The normal characteristic of a nonsynchronous

converter is to operate in the discontinuous conduction mode (DCM) at an average load current less than

one-half of the inductor peak-to-peak ripple current. Note that the amplitude of the ripple current is a function of

input voltage, output voltage, inductor value, and operating frequency, as shown in Equation 15.

During discontinuous mode operation the commanded pulse width may become narrower than the capability of

the converter to resolve. To maintain the output voltage within regulation, skipping switching pulses at light load

conditions is a natural by-product of that mode. This condition may occur if the output capacitor is charged to a

value greater than the output regulation voltage and there is insufficient load to discharge the capacitor. A

by-product of pulse skipping is an increase in the peak-to-peak output ripple voltage.

Figure 25. Steady State

Figure 26. Skipping

DESIGN HINT

If additional output capacitance is required to reduce the output voltage ripple during

DCM operation, be sure to recheck the Maximum Output Capacitance section.

A portion of the control circuitry is referenced to the SW node. To ensure jitter-free operation, it is necessary to

decrease the voltage waveform ringing at the SW node to less than 5-V peak and of a duration of less than

30-ns. In addition to following good printed circuit board (PCB) layout practices, there are a couple of design

techniques for reducing ringing and noise.

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