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SLMA002 Datasheet(PDF) 24 Page - Texas Instruments

Part # SLMA002
Description  3-A DUAL NON-SYNCHRONOUS CONVERTER WITH INTEGRATED HIGH-SIDE MOSFET AND EXTERNAL COMPENSATION
PDF  46 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

SLMA002 Datasheet(HTML) 24 Page - Texas Instruments

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Dual Supply Operation
Cascading Supply Operation
1
2
3
4
16
15
14
13
PVDD2
BOOT2
SW2
BP
PVDD1
BOOT1
SW1
GND
TPS55383
5
6
7
12
11
10
SEQ
ILIM2
FB2
EN1
EN2
FB1
OUTPUT1
OUTPUT2
V
IN
UDG-08043
8
9
COMP2
COMP1
TPS55383
,, TPS55386
SLUS818 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com
DESIGN HINT
The OCP threshold refers to the peak current in the internal switch. Be sure to add
one-half of the peak inductor ripple current to the dc load current in determining how
close the actual operating point is to the OCP threshold.
It is possible to operate a TPS5538x from two supply voltages. If this application is desired, then the sequencing
of the supplies must be such that PVDD2 is above the UVLO voltage before PVDD1 begins to rise. This level
requirement ensures that the internal regulator and the control circuitry are in operation before PVDD1 supplies
energy to the output. In addition, Output 1 must be held in the disabled state (EN1 high) until there is sufficient
voltage on PVDD1 to support Output 1 in regulation. (See the Operating Near Maximum Duty Cycle section.)
The preferred sequence of events is:
1. PVDD2 rises above the input UVLO voltage
2. PVDD1 rises with Output 1 disabled until PVDD1 rises above level to support Output 1 regulation.
With these two conditions satisfied, there is no restriction on PVDD2 to be greater than, or less than PVDD1.
DESIGN HINT
An R-C delay on EN1 may be used to delay the startup of Output 1 for a long enough
period of time to ensure that PVDD1 can support Output 1 load.
It is possible to source PVDD1 from Output 2 as depicted in Figure 27 and Figure 28. This configuration may be
preferred if the input voltage is high, relative to the voltage on Output 1.
Figure 27. Schematic Showing Cascading PVDD1 from Output 2
24
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Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS55383 TPS55386



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