SLMA002 datasheet(16/46 Pages) TI1

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5-V VOUT1

(2 V/div)

3.3-V VOUT2

(2 V/div)

T - Time - 1 ms/div

Soft Start

TPS55383

,, TPS55386

SLUS818 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com

If the SEQ pin is left floating, Output 1 and Output 2 each start ratiometrically when both outputs are enabled at

the same time. Output 1 and Output 2 soft start at a rate that is determined by the respective final output

voltages and enter regulation at the same time. If the EN1 and EN2 pins are allowed to operate independently,

then the two outputs also operate independently.

Figure 20. SEQ Pin Floating

Each output has a dedicated soft-start circuit. The soft-start voltage is an internal digital reference ramp to one of

two noninverting inputs of the error amplifier. The other input is the (internal) precision 0.8-V reference. The total

ramp time for the FB voltage to charge from 0 V to 0.8 V is about 2.1 ms. During a soft-start interval, the

TPS5538x output slowly increases the voltage to the noninverting input of the error amplifier. In this way, the

output voltage ramps up slowly until the voltage on the noninverting input to the error amplifier reaches the

internal 0.8-V reference voltage. At that time, the voltage at the noninverting input to the error amplifier remains

at the reference voltage.

During the soft-start interval, pulse-by-pulse current limiting is in effect. If an overcurrent pulse is detected, six

PWM pulses are skipped to allow the inductor current to decay before another PWM pulse is applied. (See the

Output Overload Protection section.) There is no pulse skipping if a current limit pulse is not detected.

DESIGN HINT

If the rate of rise of the input voltage (PVDDx) is such that the input voltage is too low

to support the desired regulation voltage by the time soft-start has completed, then

the output UV circuit may trip and cause a hiccup in the output voltage. In this case,

use a timed delay startup from the ENx pin to delay the startup of the output until the

PVDDx voltage has the capability of supporting the desired regulation voltage. See

Operating Near Maximum Duty Cycle and Maximum Output Capacitance for related

information.

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