PC87591L datasheet(359/437 Pages) NSC

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Host-Controlled Modules and Host Interface (Continued)

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6.2.7

Updating

The time and calendar registers are updated once per second regardless of bit 7 (SET) of CRB register. Since the time and

calendar registers are updated serially, unpredictable results may occur if they are accessed during the update. Therefore,

it is essential to ensure that reading or writing to the time storage locations does not coincide with a system update of these

locations. There are several methods to avoid this contention.

Method 1

1. Set bit 7 of CRB register to 1. This takes a “snapshot” of the internal time registers and loads them into the user copy

registers. The user copy registers are seen when accessing the RTC from outside and are part of the double buffering

mechanism. This bit may be kept set for up to 1 second, since the time/calendar chain continues to be updated once per

second.

2. Read or write the required registers (since bit 1 is set, the access is to the user copy registers). If a read operation is

performed, the information read is correct from the time bit 1 was set. If a write operation is performed, the write is only

to the user copy registers.

3. Reset bit 1 to 0. During the transition, the user copy registers update the internal registers, using the double buffering

mechanism to ensure that the update is performed between two time updates. This mechanism enables new time pa-

rameters to be loaded in the RTC.

Method 2

1. Access the RTC registers after detection of an Update Ended interrupt. This implies that an update has just been com-

pleted, and 999 ms remain until the next update.

2. To detect an Update Ended interrupt, do one of the following:

— Poll bit 4 of CRC register.

— Use the following interrupt routine:

Set bit 4 of CRB register.

Wait for an interrupt from interrupt pin.

Clear the IRQF flag of CRC register before exiting the interrupt routine.

Method 3

Poll bit 7 of CRA register. The update occurs 244

µs after this bit goes high. Therefore, if a 0 is read, the time registers remain

stable for at least 244

µs.

Method 4

Use a periodic interrupt routine to determine if an update cycle is in progress, as follows:

1. Set the periodic interrupt to the desired period.

2. Set bit 6 of CRB register to enable the interrupt from periodic interrupt.

3. Wait for the periodic interrupt to occur. This indicates that the period represented by the following expression remains

until another update occurs:

[(Period of periodic interrupt

/ 2) + 244 µs]

6.2.8

Alarms

The timekeeping function can be set to generate an alarm when the current time reaches a stored alarm time. After each

RTC time update (every 1 second), the seconds, minutes, hours, date of month and month counters are compared with their

corresponding registers in the alarm settings. If equal, bit 5 of CRC register is set. Bit 5 of CRC is sent to the MSWC as an

alarm signal. If the Alarm Interrupt Enable bit was previously set (bit 5 of CRB register), interrupt request pin is also active.

Any alarm register may be set to “Unconditional Match” by setting bits 7-6 to ‘11’. This combination, not used by any BCD

or binary time codes, results in a periodic alarm. The rate of this periodic alarm is determined by the registers that were set

to “Unconditional Match”.

For example, if all but the seconds and minutes alarm registers are set to “Unconditional Match”, an interrupt is generated

every hour at the specified minute and second. If all but the seconds, minutes and hours alarm registers are set to “Uncon-

ditional Match”, an interrupt is generated every day at the specified hour, minute and second.

PC87591L Datasheet(PDF) 359 Page - National Semiconductor (TI)

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