PC87591L datasheet(48/437 Pages) NSC

48 / 437 page

2.0 Signal/Pin Description and Configuration (Continued)

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Revision 1.07

2.2.7

Host Interface

Signal

128-Pin

LQFP

176-Pin

LQFP

I/O

Buffer

Type

Power

Well

Description

CLKRUN

I/O INPCI/OD6

VDD Clock Run. Same as PCI CLKRUN. When

high, indicates that the LPC clock will be slowed

down or stopped. In this case, the PC87591x

may pull it down to request full speed of the

clock.

GA20

O1/2

VCC Gate A20. Implemented using IOPB5 port

output. See Section 5.5.4 on page 322 for

signal operation and behavior when VDD is

down.

KBRST

O1/2

VCC Keyboard Reset Output. See Section 5.5.4

on page 322 for signal operation and behavior

when VDD is down.

LAD0-3

10-13

15-13,

I/O INPCI/OPCI VDD LPC Address-Data. Multiplexed command,

address bidirectional data and cycle status.

LCLK

INPCI

VDD LPC Clock. Practically the PCI clock (up to 33

MHz).

ECSCI

O2/12

VCC EC SCI. Generates an Embedded Controller

SCI interrupt to the chipset. This signal is

typically connected to one of the chipset GPI

inputs.

LDRQ

OPCI

VDD LPC DMA Request. Encoded Bus Master

request for LPC I/F.

LFRAME

INPCI

VDD LPC Frame. Low pulse indicates the beginning

of a new LPC cycle or the termination of a

broken cycle.

LPCPD

INPCI

VCC Power Down. Indicates that power will be shut

off on the LPC interface.

RESET1

INPCI

VCC Reset 1. A falling edge on this signal starts a

reset sequence of the PC87591x. For details,

see details in Section 3.2 on page 65.

RESET2

24/123 30/165

INCS

VDD Reset 2. A level low reset to the LPC interface

and Host Controlled Functions conﬁguration

registers and Shared Memory host registers.

For details, see Section 3.2 on page 65.

RESET2 is either assigned to one of two

optional pins or it is disabled, as deﬁned in the

protection words stored in the ﬂash memory.

See Section 2.4.1 on page 54 and

Section 4.16.6 on page 226 for the

conﬁguration of this signal.

PWUREQ

O1/2

VCC Power-Up Request.

SERIRQ

I/O INPCI/OPCI VDD Serial IRQ. The interrupt requests are

serialized over a single pin, where each IRQ

level is delivered during a designated time slot.

SMI

I/O INTS/OD12 VCC System Management Interrupt.

PC87591L Datasheet(PDF) 48 Page - National Semiconductor (TI)

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