PC87591L datasheet(68/437 Pages) NSC

68 / 437 page

3.0 Power, Reset and Clocks (Continued)

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Revision 1.07

3.3

CLOCK DOMAINS

The PC87591x has three clock domains, as shown in Table 12.

Core Domain Clock

The core clock is sourced by the HFCG. The following section gives an overview of the clock domain.

On VCC Power-Up reset, the HFCG is set to generate a 4 MHz clock. The HFCG frequency can be modified by core firm-

ware. See Section 4.18 on page 239.

On WATCHDOG reset (or Debugger interface reset), the HFCG is reset.

LPC Clock

The LPC interface is driven by the LCLK input. LCLK frequency can be up to 33 MHz. The clock CLKRUN signal may be

used as part of a power management scheme that slows the clock down; see “CLKRUN Functionality” on page 343.

RTC (32 KHz) Clock

The RTC clock is the reference for the generation of all other clocks in the PC87591x. The clock is enabled at VCC power-

up and is kept active while VPP is active. Keeping the RTC clock active significantly reduces the PC87591x wake-up time.

The RTC clock is used for time keeping in the RTC; it is also fed into the Power Management Controller (PMC), which pro-

vides the clock to other functions (such as TWD and ACM) that are active at all times (including Idle).

Table 12. PC87591x Clock Domains

Clock Domain

Frequency

Source

Usage

Core

See Section 4.18

on page 239

HFCG

Core domain and host-core interface

LPC

Up to 33 MHz

LPC clock input

LPC bus interface

RTC

32 KHz

Clock input or on-chip oscillator1

1. See Section 6.2.3 on page 356 and Section 6.2.4 on page 357.

RTC, HFCG, TWD, PMC, ACM

PC87591L Datasheet(PDF) 68 Page - National Semiconductor (TI)