PC87591L datasheet(67/437 Pages) NSC

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3.0 Power, Reset and Clocks (Continued)

Revision 1.07

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During a Warm reset, the PC87591x responds as follows:

●

Terminates core executed instructions

●

Discards results not yet written to memory

●

Eliminates any pending core interrupts and traps

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Clears the internal latch for the core domain’s edge-sensitive external interrupt

●

Deactivates the external bus control signals WR(0-1), SEL(0-1), SELIO, RD and BST(0-2)

●

Puts the address A(0-19) and data D(0-15) buses in TRI-STATE

●

Switches to core domain’s Active mode

●

Loads default values into registers, with the exception of:

— The Mobile System Wake-Up Control (MSWC) and RTC registers retained by VPP.

— Some registers that are speciﬁcally noted to be cleared only by other events

●

Resets the Debugger interface, except for TAP controller

During Warm reset, strap pins are not sampled and the configuration determined at VCC power-up is unaffected by subse-

quent Warm resets.

The PC87591x core domain and some parts of the host-core interface functions can operate when RESET1 is still asserted

(low). Some parts of the Host Domain Functions that are reset by the Host Domain reset (see following section) are kept

reset as long as RESET1 is asserted.

3.2.5

Host Domain Reset

Using RESET2 Input

The RESET2 input signal is enabled as an alternate function on one of two pins. The Protection Word in the flash memory

is used to define whether the RESET2 input is enabled and, if so, on which of the two pins. See Section 4.16.6 on page 226

for details on RESET2 input configuration.

Note that enabling RESET2 input on either of the signals causes that pin to be used as an input GPIO with an interrupt input

associated with it. It is recommended to use this interrupt function to interrupt the core when a RESET2 event occurs and

to use the interrupt routing to stop activities and resume default values to some system elements not directly reset by the

event.

Host Domain Reset Actions

The reset actions on the host domain are broken into two categories that depend on the reset event source; some of the

actions may happen for both these reset source types and thus are named Host Domain Rest.

Host Domain Hardware Reset: While RESET1 is active, RESET2 is also active if VDD is on or during VDD power-up.

Host Domain Hardware reset performs the following actions:

●

It brings the LPC interface state machine to its inactive state.

●

It resets all SuperI/O conﬁguration registers except for those that are battery-backed (see Section 6.1.8 on page 343).

●

It resets Shared Memory Host Controlled registers

Host Domain Software Reset: This reset is triggered by a write of 1 to bit 1 in SIOCF1 register in the SuperI/O Configura-

tion registers.

Host Domain Software reset performs the following actions:

●

It resets all SuperI/O conﬁguration registers except those noted to be protected from software reset (i.e., bits that are

locked from write accesses).

●

It resets Mobile System Wake-Up Control (MSWC) bits and RTC bits marked to be reset by software.

Note that lock bits and memory protect bits are not reset by software reset; instead, they require a hardware reset to unlock

them; this requirement protects these bits from any faulty or malicious software.

For more details, see Section 6.1.3 on page 341.

Host Domain Reset: This term is used when a bit is reset by either a Host Domain Hardware reset or Host Domain Soft-

ware reset.

PC87591L Datasheet(PDF) 67 Page - National Semiconductor (TI)

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