PC87591L datasheet(86/437 Pages) NSC

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4.0 Embedded Controller Modules (Continued)

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Revision 1.07

4.1.11 Usage Hints

The following usage hints help configure the BIU to maximize PC87591x performance and avoid contention on the data bus.

1. In IRE environment, access time to the internal flash can use zero wait and zero hold cycles or fast reads depending on

the CLK frequency set for the core and its peripherals (see “Flash Read, Write and Erase Time” on page 222).

Flash sections 0 and 1 (fast zone) and Section 2 (slow zone) can use a fast read bus cycle through the operation fre-

quency of the PC87591x; therefore, program SZCFG1 fields to be: WAIT=000, HOLD=00, BRE=0, WBE=0, BW=1,

FRE=1.

When Section 2 (slow zone) can operate with a fast read bus cycle, program SZCFG2 fields to be: WAIT=000,

HOLD=00, BRE=0, WBE=0, BW=1, FRE=1.

When Section 2 (slow zone) needs to operate with normal read and zero wait, program SZCFG2 fields to be: WAIT =000,

HOLD=00, BRE=0, WBE=0, BW=1, FRE=0.

2. To avoid contention on the data bus when a read bus cycle (no Thold clock cycles) in one zone is followed by a read bus

cycle in another zone, program IPST and IPRE in the different memory (I/O) zones as follows:

IPRE (Idle Before Bus Cycle). Inserts an idle cycle before the current bus cycle when this bus cycle is in a new

zone.

0: No idle cycle inserted

1: Idle cycle inserted

FRE (Fast Read Enable).

0: Disabled - Normal read bus cycle takes at least two clock cycles

1: Enabled - Normal read bus cycle takes one clock cycle

15-12 Reserved.

Zone

IPRE

IPST

Zone 0

Zone 1

Zone 2

0/11

1. Set IPRE when the zone is con-

ﬁgured for fast read.

Zone I/O

2. An IPRE is forced always for

Zone I/O.

Bit

Description

PC87591L Datasheet(PDF) 86 Page - National Semiconductor (TI)