PC87591L datasheet(65/437 Pages) NSC

65 / 437 page

3.0 Power, Reset and Clocks (Continued)

Revision 1.07

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3.2

RESET SOURCES AND TYPES

The PC87591x has several input reset types:

●

VPP Power-Up reset (for VPP supplied functions only)

Activated when either VCC or VBAT is powered up after both have been off.

●

VCC Power-Up reset

Activated when VCC is powered up.

●

Warm reset

Activated on RESET1 input falling edge.

●

WATCHDOG and Debugger Interface resets:

— WATCHDOG reset

Activated on request from the TWD module (WATCHDOG signal is asserted); see Section 4.10 on page 164.

— Debugger Interface reset

Activated on request from the Debugger Interface module used during debug and ﬂash updates; see Section 4.19

on page 248.

●

Host Domain reset

This is divided into two sub-groups: Host Domain Hardware and Host Domain Software reset. Combinations consist-

ing of the ﬂowing events are used to trigger these reset operations:

— RESET1 active

— When VDD is active, RESET2 is active

— On VDD power-up

— A Software reset triggered by a write of 1 to bit 1 of SIOCF1 register in the SuperI/O Conﬁguration registers; see

Section 6.1.8 on page 343

Unless otherwise noted, reset references throughout the PC87591x modules default to the following types:

●

For VPP retained functions: VPP Power-Up reset

●

For core domain functions and host-core interface functions: VCC Power-Up reset, Warm reset, WATCHDOG reset,

Debugger Interface reset and Software reset

●

For host domain functions: Host Domain reset

VCC

GND

Digital Ground Plane

Analog

AVCC

C3 0.1

0.1

AGND

Analog Ground Plane

Power

AD0

AD9

VIN0

VIN9

VIN

10-100

(3.3V)

DA0

DA3

VOUT0

VOUT3

Suspend

Digital

Power

(3.3V)

VDD

0.1

BAT

VBAT

(3.3V)

Digital

Power

Host

Backup

Power

0.1

PC87591x

Figure 11. PC87591x Power Supply Connection

KBVIN0

KBVIN7

KBVIN

KBSIN0

KBSIN7

PC87591L Datasheet(PDF) 65 Page - National Semiconductor (TI)

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