PC87591L datasheet(46/437 Pages) NSC

46 / 437 page

2.0 Signal/Pin Description and Configuration (Continued)

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Revision 1.07

IOPA7-0

33-26

43,

40-36,

33-32

I/O INTS/O3/6

VCC General-Purpose I/O Ports. The GPIO

registers are accessible by the core for read,

write and conﬁguration. Each of these GPIO

signals can be individually conﬁgured to be

input or output. The pins may be used as GPIO

or assigned to their respective alternate

functions. See Section 2.4 on page 54 for

assignment of GPIO pins to alternate functions.

See Section 4.5 on page 113 for further details

on the GPIO pins and their functionality.

IOPD1-0

23-22

29, 26

IOPB7-3

123,

6-5,

122-121

165,

6-5,

164-163

I/O INTS/O1/2

VCC

IOPC6-1

2-1,

128-125

176-175

172-169

IOPH3-0

95-92

127-124

IOPI7-0

109-102 147-144

141-138

IOPJ7-2

N/A

76-75

70-71

63-62

IOPJ1-0

111-110 151-150

IOPK7-0

N/A

120-121

129-130

134-135

142-143

IOPL4-0

N/A

48,

103-104

112-113

IOPM7-0

N/A

28-27,

4-3,

156-155

149-148

IOPB2-0

120,

114-113

162,

154-153

I/O INTS/O2/4

VCC

IOPC7

IOPD7-4

N/A

55-54,

42-41

I/O INTS/O2/12 VCC

IOPD3-2

25-24

31-30

IOPF7-0

89-82

119-114

111-110

IOPH7-4

99-96

133-131

128

IOPC0

124

168

O3/6

VCC General-Purpose Output Port IOPC0. IOPC0

is are targeted for use as power supply control

for the power supply unit. It is accessible by the

core for write and conﬁguration. On VCC Power-

Up reset, the default state TRI-STATE; it is not

affected by other types of reset. See Section 4.5

on page 113 for further details on these GPIO

pins and their functionality.

Signal

128-Pin

LQFP

176-Pin

LQFP

I/O

Buffer

Type

Power

Well

Description

PC87591L Datasheet(PDF) 46 Page - National Semiconductor (TI)

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