PC87591L datasheet(14/437 Pages) NSC

14 / 437 page

Table of Contents (Continued)

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Revision 1.07

4.16.4

Flash Access and Control .......................................................................................... 224

4.16.5

Parallel Flash Interface .............................................................................................. 226

4.16.6

Flash Protection ......................................................................................................... 226

4.16.7

Flash Interface Registers ........................................................................................... 228

Information Block Access Index Register (IBAI) ................................................ 228

Information Block Data Register (IBD) ............................................................... 229

Flash Core Write Protect Register 0 (FCWP0) .................................................. 229

Flash Memory Control Register (FLCR) ............................................................ 230

Flash Memory Status Register (FLSR) .............................................................. 231

Flash Memory Pre-Scaler Register (FLPSLR) ................................................... 231

Flash Memory Start Time Register (FLSTART) ................................................. 232

Flash Memory Transition Time Register (FLTRAN) .......................................... 232

Flash Memory Program Time Register (FLPROG) ............................................ 232

Flash Memory Page Erase Time Register (FLPERASE) ................................... 233

Flash Memory Section Erase Time Register (FLSERASE) ............................... 233

Flash Memory End Time Register (FLEND) ...................................................... 233

Flash Memory Section Erase End Time Register (FLSEND) ............................ 234

Flash Memory Recovery Time Register (FLRCV) ............................................. 234

4.17

POWER MANAGEMENT CONTROLLER (PMC) ................................................................... 235

4.17.1

Features .................................................................................................................... 235

4.17.2

The Core Domain Power Modes ............................................................................... 235

4.17.3

Switching Between Power Modes ............................................................................. 236

Decreasing Power Consumption ....................................................................... 236

Increasing Activity .............................................................................................. 236

Power Mode Switch Protection .......................................................................... 237

4.17.4

The Power Management Controller Status Register (PMCSR) ................................. 237

4.17.5

Usage Hints ............................................................................................................... 238

4.18

HIGH-FREQUENCY CLOCK GENERATOR (HFCG) ............................................................. 239

4.18.1

Features .................................................................................................................... 239

4.18.2

Functional Description ............................................................................................... 239

4.18.3

HFCG States ............................................................................................................. 240

PMC Enabled SuperI/O Disabled State ............................................................. 240

SuperI/O Enabled State ..................................................................................... 242

4.18.4

The Programmable Pre-Scaler: Core Domain Clock Generation .............................. 242

4.18.5

State Transitions ........................................................................................................ 242

4.18.6

48 MHz Clock Monitor ............................................................................................... 243

4.18.7

HFCG Registers ....................................................................................................... 243

HFCG Register Map .......................................................................................... 243

HFCG Control Register 1 (HFCGCTRL1) .......................................................... 244

HFCGM Low Value Register (HFCGML) ........................................................... 245

HFCGM High Value Register (HFCGMH) ......................................................... 245

HFCGN Value Register (HFCGN) ..................................................................... 245

HFCGI Low Value Register (HFCGIL) ............................................................... 246

HFCGI High Value Register (HFCGIH) ............................................................. 246

HFCG Pre-Scaler Register (HFCGP) ................................................................ 246

HFCG Control Register 2 (HFCGCTRL2) .......................................................... 247

4.19

THE DEBUGGER INTERFACE ............................................................................................... 248

4.19.1

Features .................................................................................................................... 248

4.19.2

Structure .................................................................................................................... 248

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