PC87591L datasheet(88/437 Pages) NSC

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Embedded Controller Modules (Continued)

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Table 15. DMA Channel Assignment

4.2.4

Transfer Types

The DMAC uses two data transfer modes, direct (fly-by) and indirect (memory-to-memory). The choice of mode depends on

the correlation between the source and destination bus lengths, the required bus performance and the peripheral structure

(as indicated in Table 15).

Direct (Fly-By) Transfers

Figure 27. DMAC Direct Bus Cycle Followed by a Core Bus Cycle

In Direct mode, each data item is transferred using a single bus cycle without reading the data into the DMAC. It provides

the fastest transfer rate, but it requires identical source and destination bus widths.

Data transfer cannot occur between two memory elements. One of the elements must be the I/O device that requested the

DMA transfer. This device is referred to as the implied I/O device. The other element can be either memory or another I/O

device and is referred to as the addressed I/O device.

The appropriate DMA acknowledge signal for each channel is asserted during the bus cycle.

If the bus policy is “intermittent”, maximum throughput is one transaction every three clock cycles. If bus policy is “continu-

ous”, maximum throughput on the internal core bus is one transaction every two clock cycles.

Since only one address is required in Direct mode, this address is taken from the corresponding ADCAn counter. The DMAC

Channel generates either a read or a write bus cycle according to the setting of DIR bit in DMACNTLn register.

When DIR bit is 0, a read bus cycle from the addressed device is performed, and the data is written to the implied I/O device.

When DIR bit is 1, a write bus cycle to the addressed device is performed, and the data is read from the implied I/O device.

The configuration of either address freeze or address update (increment or decrement) is independent of the number of

transferred bytes, transfer direction, or number of bytes in each DMAC transfer cycle. All these can be configured for each

channel by programing the appropriate control register.

The number of bytes transferred in each cycle is taken from TCS bit in DMACNTLn register. After the data item has been

transferred, the BLTCn counter is decremented by one. The ADCAn counter are updated according to INCAn field and ADA

bit in DMACNTLn register.

Channel

Usage

Mode

Enable Control

Interrupt

USART Receive

Indirect

USART registers

DMA_INT0

USART Transmit

Indirect

USART registers

DMA_INT1

Reserved

Indirect

Reserved

Indirect

CLK

DMRQi

ADDR

DMACKi

Tidle

Bus State

ADCA

PC87591L Datasheet(PDF) 88 Page - National Semiconductor (TI)

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